Memory Interface IP
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Memory Interface IP
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958
Memory Interface IP
from 61 vendors
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HBM4 Memory Controller
- Supports HBM4 memory devices
- Supports all standard HBM4 channel densities (up to 32 Gb)
- Supports up to 10 Gbps/pin
- Refresh Management (RFM) support
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TSMC CLN4P 4nm DDR5 PHY - 6400Mbps
- Supports DDR5
- DFI 5.1 compliant
- Supports x4, x8 and x16 DRAMs
- Up to 72 bits wide and up to 4 ranks
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ReRAM NVM in 130nm CMOS, S130
- Technology: 130nm, SkyWater S130
- Mask Adder: 2
- Supply Voltage: 1.8V Read, 1.8V+3.3/3.6V Program
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LPDDR5X DDR Memory Controller
- JEDEC LPDDR5X/LPDDR5 devices compatible
- Data rates up to 8533Mbps
- Multiple ARM AMBA AXI4/AHB/APB & Custom interfaces
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ONFI 5.0 NAND FLASH Controller Compliant to JEDEC
- ONFI v5.0 compliant + Up to 2.4GByte/s.
- All I/O modes implemented + SDR + NV-DDR + NV-DDR2/3 + NV-LPDDR4
- Wide hardware support + Four 8-bit data paths + 8 NAND targets each + Data bus inversion.
- Full PLL support + PLL within PHY + 10MHz SDR + 1.2GHz NV-LPDDR4 + Everything in between
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ONFI Flash Controller
- AXI System Interface
- NAND Flash
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Universal NVM Express Controller (UNEX)
- Compliant to NVM Express 1.1
- Support for configurable number of IO Queues
- Support for configurable Queue depth
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NVM Express IP Core
- High performance PCIe SSD with no host CPU load
- Cost reduction thanks to interface standardization
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
- Programmable timing
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DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP
- Compliant with JEDEC standard for LPDDR5/4/3, DDR4/3
- DRAM rank of up to 4
- Lock-step-based controlling of multiple DRAM devices up to x64 DQ width
- Support for dynamic DRAM frequency scaling
