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SAS IP

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Search (10)
Compare 10 SAS IP from 4 vendors (1 - 10)
  • SAS Initiator, 12G, 4 Ports, 48 Gbps, AXI Interface
    • SAS & SATA Speed Negotiation and OOB
    • SAS 1.5, 3.0, 6.0 and 12.0 Gbps support
    • SATA 1.5, 3.0 and 6.0 Gbps support
    • Native 32 bit PHY interface
    Block Diagram -- SAS Initiator, 12G, 4 Ports, 48 Gbps, AXI Interface
  • Bi-directional High speed interface lane up to 12.5Gbps
    • High data rate (Up to 12.5Gbps per lane)
    • Programmable receiver frontend
    • Programmable transmitter
    • 5-bit controlled digital delay line in the receiver for high-speed clock
  • SAS Initiator, 12G, 4 Ports, 48 Gbps
    • SAS & SATA Speed Negotiation and OOB
    • SAS 1.5, 3.0, 6.0 and 12.0 Gbps support
    • Native 32 bit PHY interface
  • SAS Initiator, 12G, Wide, 4 Ports, 48 Gbps
    • SAS & SATA Speed Negotiation and OOB
    • SAS 1.5, 3.0, 6.0 and 12.0 Gbps support
    • SATA 1.5, 3.0 and 6.0 Gbps support
  • SAS Initiator, 12G, 4 Ports, 48 Gbps, SATA Host
    • SAS & SATA Speed Negotiation and OOB
    • SAS 1.5, 3.0, 6.0 and 12.0 Gbps support
    • SATA 1.5, 3.0 and 6.0 Gbps support
  • SAS 4 Port 12G Recorder
    • High Speed Data Recording
    • Up to 4 Ports
    • SAS 1.5, 3.0, 6.0 and 12.0 Gbps support
  • SAS 1-to-1 Speed Bridge with Sandbox
    • • Allows users to intercept data between the SAS Host and Device
    • • Fully compliant to SAS Gen-3 (12GHz) industry specifications.
    • • With correct FPGA, Bridge is capable of SAS Gen-3 (12GHz)
    • • Industry proven and compliant SAS interfaces
  • SAS Target Core
    • Fully compliant to the SAS 3.0Gb/s, 6.0 and 12.0Gb/s industry specifications
    • Processor specific interfaces for register access
    • Supports either SerDes, PIPE, or SAPIS interface
    • Synchronous design for easy integration
  • SAS Initiator Core
    • Fully compliant to the SAS 3.0, 6.0 and 12.0 Gb/s industry specifications
    • Processor specific interfaces for register access
    • Supports either SerDes, PIPE, or SAPIS interface
    • Synchronous design for easy integration
  • SAS Initiator IP
    • Supports SPL 1.0/2.0/3.0/4.0/5.0 Specs
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
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Semiconductor IP