On-chip ESD protection for High Voltage applications in TSMC BCD technology

B. Keppens, K. Verhaege from SOFICS
EETimes (3/5/2012 10:14 AM EST)

Introduction

A growing set of IC applications require a high voltage interface. Examples include power management, power conversion and automotive chips with interfaces typically between 12 V and 100 V. Also, mobile devices like cell phones and personal navigation devices today include interfaces above 10 V to, e.g., control and sense MEMS gyroscopic or compass sensors. And most LCD/OLED display technologies require driving voltages between 10 and 40 V. Besides the power, MEMS, and display interfaces, many devices include some sort of motor like the optical zoom lens and shutter control of digital cameras or the ‘silent mode’ vibrator in cell phones.

Though these applications represent fast-growth markets, the underlying silicon process technologies lack standardized high-performance ESD solutions. The purpose of ESD protection is to provide a safe, robust current path while limiting the voltage drop below the critical voltage determined by the circuit to be protected. Today, different protection clamp types are used in the industry, each with significant performance and cost burdens that prevent generic use. The main problems with traditional solutions are high leakage current, large silicon area consumption, and extensive custom (trial and error) development cycles for each process/fab change.

Despite the efforts from the ‘ESD council’ to reduce the component-level ESD performance levels [1-2], there is an opposing trend to push system-related ESD/latch-up requirements down to the IC design level in order to reduce system failures and improve user safety [3-4]. This is most prevalent in automotive, industrial and consumer electronics markets. OEMs request very robust and latch-up immune on-chip ESD protection devices [5].

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