Defining standard Debug Interface Socket requirements for OCP-compliant multicore SoCs: Part 2
By Neal Stollon, HDL Dynamics, Bob Uvacek, Pixelworks, and Gilbert Laurenti, Texas Instruments
Jul 16 2007 (0:05 AM), Embedded.com
Jul 16 2007 (0:05 AM), Embedded.com
As discussed in Part 1 in this series, in the same way the OCP data socket is a superset for the different bus interfaces and data structures, an OCP debug socket will provide a superset of the debug solutions based on standardized libraries of debug IP blocks that interact with the debug sockets signals. This allows the following:
-
Signal level observation (bus and system trace) and control (triggering)
-
Consistent (multiple) processor software debugger and bus traffic observation interfaces
-
Special debug features for security islands, voltage islands, gated clock islands etc.
-
New classes of debug errors (which are different from system errors.
To read the full article, click here
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related White Papers
- Defining standard Debug Interface Socket requirements for OCP-Compliant multicore SoCs: Part 1
- Standard Debug Interface Socket Requirements For OCP-Compliant SoC
- Standard socket interface tapped
- Multicore SoCs change interconnect requirements