Defining standard Debug Interface Socket requirements for OCP-Compliant multicore SoCs: Part 1

Enabling a robust on-chip debug capability is being recognized as an important Design for Debug (DFD) capability for complex SoC and having DFD standardization makes the Open Core Protocol (OCP) more attractive as a SoC platform.

Debug signal interfaces are outside of the scope of the current OCP 2.2 specification, however the OCP-IP Steering Committee has recognized that add additional signal interface definitions to support on-chip debug make OCP an "Even More Complete Socket."

On-chip debug addresses the visibility and control needed for improved analysis of operations and interactions within OCP architectures, at different stages in design flows, while providing a common set of debug options and consistent signal interfaces.

OCP Debug definitions also provide a common set of interfaces that allow better support from debug probe and tool venders and EDA tool venders and to enable convergence of debug and verification activities.

The initial goal of the working group is to document a common set of Debug Guidelines and socket level signal models that address the range of simple to more complex debug of OCP based systems.

These include debug configurations and strategies that comprehend multiple clock domains, power management domains, security domains, etc. required in modern SoC and embedded systems design. Conceptually, the architecture avoids the need for a separate debug bus to keep a simple modular on-chip IP structure, in line with the OCP-IP architectural philosophy.

Where possible the debug specification leverages signals and interfaces defined in other OCP specifications. As an example, JTAG signals were defined in OCP2.0 as a primary debug interface, and are therefore referenced as a default option for on-chip debug integration.

The intent however is not to limit implementation to 1149.1 JTAG. Interfaces with higher bandwidth options to enable better debug support are often needed, with some options being Nexus and MIPI interfaces, AJTAG, SerDes (Aurora), other interfaces, etc.

As another option for more directly integrated debug control interfaces, such as memory mapped debug options using an embedded processor for debug block configuration and control are also supported.

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