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LPDDR3 Controller IP

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Search (14)
Compare 14 LPDDR3 Controller IP from 4 vendors (1 - 10)
  • LPDDR3 Synthesizable Transactor
    • Supports 100% of LPDDR3 protocol standard JESD209-3, JESD209-3B and JESD209-3C
    • Supports all the LPDDR3 commands as per the specs
    • Supports up to 32GB device density
    • Supports the following devices:
    Block Diagram -- LPDDR3 Synthesizable Transactor
  • LPDDR3 DFI Synthesizable Transactor
    • Compliant with DFI version 3.1 or higher Specifications.
    • Supports LPDDR3 devices compliant with JEDEC LPDDR3 SDRAM Standard JESD209-3.pdf, JESD209-3B.pdf and JESD209-3C.pdf
    • Supports for Read data-eye training.
    • Supports for Read gate training.
    Block Diagram -- LPDDR3 DFI Synthesizable Transactor
  • LPDDR3 DFI Verification IP
    • Compliant with DFI version 3.1 or higher Specifications.
    • Supports LPDDR3 devices compliant with JEDEC LPDDR3 SDRAM Standard JESD209-3.pdf, JESD209-3B.pdf and JESD209-3C.pdf
    • Supports for Read data-eye training
    • Supports for Read gate training
    Block Diagram -- LPDDR3 DFI Verification IP
  • LPDDR3 Controller IIP
    • Supports 100% of LPDDR3 protocol standard JESD209-3, JESD209-3B and JESD209-3C.
    • Compliant with DFI version 3.1 or higher Specification.
    • Supports all the LPDDR3 commands as per the specs.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    Block Diagram -- LPDDR3 Controller IIP
  • LPDDR Controller IIP
    • Supports LPDDR protocol standard and JESD209A-1 and JESD209B Specification
    • Compliant with DFI version 2.0 or higher Specification.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    • Supports controllable outstanding transcations for AXI write and read channels
    Block Diagram -- LPDDR Controller IIP
  • LPDDR3 Assertion IP
    • Specification Compliance
    • Supports all signal level checks including X detection
    • Support for check-points include power on, Initialization and power off rules,
    • Support for state based rules, Active Command rules,
    Block Diagram -- LPDDR3 Assertion IP
  • LPDDR3 DFI Assertion IP
    • Specification Compliance
    • Compliant with DFI version 3.1 or higher Specifications.
    • Supports LPDDR3 devices compliant with JEDEC LPDDR3 SDRAM Standard JESD209-3.pdf, JESD209-3B.pdf and JESD209-3C.pdf.
    • Supports for Read data-eye training.
    Block Diagram -- LPDDR3 DFI Assertion IP
  • LPDDR Controller
    • Memory controller interface complies with DFI standard up to 5.0
    • Application-optimized configurations for fast time to delivery and lower risk
    • Sideband and in-line SEC/DED ECC
    • Supports advanced RAS features including error scrubbing, parity, etc.
    • Compliant to LPDDR5/4X/4/3 protocol memories
    • Priority per command on Arm®AMBA® 4 AXI, AMBA 3 AXI
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