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Interconnect IP for TSMC

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Compare 810 Interconnect IP for TSMC from 38 vendors (1 - 10)
  • PCIe 3.1 Controller with AXI
    • Compliant with the PCI Express 3.1/3.0, and PIPE (16- and 32-bit) specifications
    • Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
    • Supports Endpoint, Root-Port, Dual-mode configurations
    • Supports x16, x8, x4, x2, x1 at 8 GT/s, 5 GT/s, 2.5 GT/s speeds
    • Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
    • Supports many ECNs including LTR, L1 PM substates, etc.
    Block Diagram -- PCIe 3.1 Controller with AXI
  • I2C Controller IP – Master, Parameterized FIFO, AXI Bus
    • The DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0 AXI System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
    • The DB-I2C-M-AXI is a Master I2C Controller that controls the Transmit or Receive of data to or from slave I2C devices. Figure 1 depicts the system view of the DB-I2C-M AXI Controller IP Core embedded within an integrated circuit device.
    Block Diagram -- I2C Controller IP – Master, Parameterized FIFO, AXI Bus
  • I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus

    • The DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AMBA AHB Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).

      The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.

      The DB-I2C-MS-AHB is a Master / Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.

    Block Diagram -- I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus
  • I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus

    • The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).

      The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.

      The DB-I2C-MS-APB is a Master/Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.

    Block Diagram -- I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus
  • I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
    • The DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AMBA AXI Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).
    • The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
    • The DB-I2C-MS-AXI is a Master / Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.
    Block Diagram -- I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
  • Complete USB Type-C Power Delivery IP
    • Mixed signal Analog Front End Macros for 65n, 130n, 150nm, and 180n technologies.
    • RTL code from AFE to I2C compatible register set.
    • Stand alone C code for Protocol, Device Policy Manager, and System Policy Manager.
    • IP demonstration & development board, with compliance reports. 
    • Full chip integration of USB Type-C, and associated software.
    Block Diagram -- Complete USB Type-C Power Delivery IP
  • Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.116 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.3 mW/Gbps (@6Gbps) including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    Block Diagram -- Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
  • USB 2.0 PHY
    • Designed to the USB 2.0 specification, and operates at High Speed (480Mbps), Full Speed (12Mbps), and Low Speed (1.5Mbps)
    • Complies with the UTMI v1.05 specification
    • Multiple reference clock supported from 9.6MHz up to 52MHz
    • 8-bit 60MHz and 16-bit 30MHz parallel interfaces
    • Battery Charging Specification v1.2
    Block Diagram -- USB 2.0 PHY
  • 10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
    • Supports USB 3.1, PCIe 3.0/2.0/1.0, DP-TX v1.4/ eDP-TX v1.4b, SATA 3, 10G-KR and SGMII
    • Supports PCIe L1 sub-states
    • Supports SRIS and internal SSC generation
    • Supports internal and external clock sources with clock active detection
    Block Diagram -- 10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
  • PDM-to-PCM Conversion with AMBA Interface
    • SNR 100dB; THD -100dB
    • PDM (pulse-density modulated) Input
    • PCM (pulse-code modulated) output
    Block Diagram -- PDM-to-PCM Conversion with AMBA Interface
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