MIPI D-PHY Universal IP in TSMC 65GP

Overview

The MXL-D-PHY-UNIV-T-65GP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.1. The PHY can be configured as a MIPI Master or MIPI Slave supporting camera interface CSI-2 and display interface DSI/DSI-2 applications.

Key Features

Supports MIPI Alliance Specification for D-PHY Version 2.1
Backward compatible with MIPI Specifications for D-PHY v1.2, and v1.1
Consists of 1 Clock lane and 4 Data lanes
Embedded high performance, highly programmable, PLL
Supports both high speed and low-power modes
80 Mbps to 1.5 Gbps data rate per lane without Deskew calibration
Up to 2.5 Gbps data rate per lane with Deskew calibration
10 Mbps data rate in low-power mode
Low power dissipation
Testability support including internal loopback
Calibrator for resistance termination

Benefits

The IP can be configured as a MIPI Master or MIPI Slave optimized for CSI-2 (Camera Serial Interface), and DSI (Display Serial Interface) applications.

Block Diagram

Applications

Mobile
Displays
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

TSMC 65GP

Maturity

Upon Request

Availability

Now

Request Info