The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v1.1. The IP can be configured as a MIPI Master or MIPI Slave optimized for CSI-2 (Camera Serial Interface), and DSI (Display Serial Interface) applications. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control
MIPI D-PHY Universal IP in TSMC 40LP-eF
Overview
Key Features
- Consists of 1 Clock lane and up to 4 Data lanes.
- Supports MIPI® Alliance Specification for D-PHY Version 1.1.
- Supports both high speed and low-power modes.
- 80 Mbps to 1.5 Gbps data rate in high speed mode.
- 10 Mbps data rate in low-power mode.
- High Speed Serializers and Deserializers included.
- Low power dissipation.
- Loopback testability support.
- Optional resistance termination calibrator.
Benefits
- Supports both MIPI CSI-2 and MIPI DSI, as a transmitter and receiver
Block Diagram

Video
Hercules Microelectronics HME-H1D03 FPGA featuring Mixel's MIPI D-PHY IP
In this Mixel customer demo video, we see Mixel’s MIPI D-PHY IP integrated into the Hercules Microelectronics HME-H1D03 FPGA, configured as a Human Machine Interface (HMI) solution based, which can be used for smart home appliances such as refrigerator, ventilator, air conditioning control panel. In this demo, we see the GUI for refrigerator control. Mixel provided our MIPI D-PHY Universal IP. For more information, visit: https://mixel.com/mixel-d-phy-ip-hme-fpga-processor/ For more information about the HME-H1D03 FPGA, visit: http://en.hercules-micro.com/content/details86_596.html
Applications
- Mobile
- Displays
- Cameras/Sensors
- IoT
- VR/AR/MR
- Consumer electronics
- Automotive
Deliverables
- Specifications
- GDSII
- LVS netlist
- LEF file
- IBIS Model
- Verilog Model
- Timing Model
- Integration Guidelines
- RTL
- Documentation
- One year support
Technical Specifications
Foundry, Node
TSMC, 40LP - eF
Maturity
Upon Request
Availability
Now
TSMC
Pre-Silicon:
40nm
LP