NEC architects - around mixed-signal roadblocks
February 12, 2010
Two papers presented by NEC Electronics at the International Solid State Circuits Conference this week illustrate the extent to which mixed-signal designers are turning to architectural innovation to go where scaling can no longer take them. An all-digital phase-locked loop (PLL) breaks out of the envelope to reach a new power-vs.-noise operating point. And a 16 Gbit transceiver design in 90nm CMOS demonstrates that architectural changes can overcome fundamental timing limits in decision-feedback equalizers (DFEs.)
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