Forward Error Correction IP
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Forward Error Correction IP
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84
Forward Error Correction IP
from 18 vendors
(1
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10)
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VESA DisplayPort 2.0 FEC RX
- VESA DisplayPort 2.0 compliant
- Reed Solomon RS (198,194) FEC, 8-bit symbols
- Multiple symbols per clock
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VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- Complete DisplayPort™ 1.4 Receiver solution with support for VESA Display Stream Compression (DSC)
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HDMI 2.1 Forward Error Correction (FEC) Receiver
- HDMI 2.1 compliant
- Reed-Solomon RS(255,251) FEC, 8-bit symbols
- Supports 3-lane and 4-lane operation
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Viterbi Decoder
- Hard or soft decoder with configurable soft bit widths
- Parameterisable generator polynomials
- Parameterisable code Constraint length
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Polar Encoder / Decoder for 3GPP 5G NR
- Fully compliant with the 3GPP NR standard for PUCCH, PUSCH, PDCCH and PBCH. Supports the full range of uncoded and encoded block sizes
- Implements the entire Polar encoding and decoding chain in 3GPP TS38.212
- High error correction performance from Polar PC/CRC-aided decoder core
- Tightly integrates the components in the chain to reduce area usage and latency
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DOCSIS 3.1 LDPC Decoder (PLC / NCP / Data)
- Soft-Decision Demapper, Derandomizer, Deinterleaver, Depuncturer, and LDPC Decoder are included
- Support for 4k and 8K FFT sizes
- Support for 16-QAM modulation
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66/2112 Codec for Cyclic Code (2112,2080)
- Small Size
- Implements FEC Sublayer for 10GBASE-R (section 74 of the IEEE 802.3 standard)
- 10G/40G/100G Ethernet MAC-friendly interface
- Practically self-contained: requires only memory for one 2112-bit block in the decoder.
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SDA OCT V3.0 Encoder and Decoder
- Compliant with "Optical Communications Terminal (OCT) Standard Version 3.0, Document ID: SDA-9100-0001-05, August 2021"
- Support for payload code rates 11/13, 22/29, 2/3, 1/2, and uncoded data
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DVB-GSE Encapsulator and Decapsulator
- Compliant with ETSI TS 102 606-1 V1.2.1 (Annex D, DVB-GSE Lite)
- Support for multi-protocol encapsulation (IPv4, IPv6, MPEG, Ethernet, etc.)
