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Forward Error Correction IP

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Compare 83 Forward Error Correction IP from 17 vendors (1 - 10)
  • VESA DisplayPort 2.0 FEC RX
    • VESA DisplayPort 2.0 compliant
    • Reed Solomon RS (198,194) FEC, 8-bit symbols
    • Multiple symbols per clock
    Block Diagram -- VESA DisplayPort 2.0 FEC RX
  • VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
    • Complete DisplayPort™ 1.4 Receiver solution with support for VESA Display Stream Compression (DSC)
    Block Diagram -- VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
  • HDMI 2.1 Forward Error Correction (FEC) Receiver
    • HDMI 2.1 compliant
    • Reed-Solomon RS(255,251) FEC, 8-bit symbols
    • Supports 3-lane and 4-lane operation
    Block Diagram -- HDMI 2.1 Forward Error Correction (FEC) Receiver
  • Viterbi Decoder
    • Hard or soft decoder with configurable soft bit widths
    • Parameterisable generator polynomials
    • Parameterisable code Constraint length
    Block Diagram -- Viterbi Decoder
  • Polar Encoder / Decoder for 3GPP 5G NR
    • Fully compliant with the 3GPP NR standard for PUCCH, PUSCH, PDCCH and PBCH. Supports the full range of uncoded and encoded block sizes
    • Implements the entire Polar encoding and decoding chain in 3GPP TS38.212
    • High error correction performance from Polar PC/CRC-aided decoder core
    • Tightly integrates the components in the chain to reduce area usage and latency
    Block Diagram -- Polar Encoder / Decoder for 3GPP 5G NR
  • 66/2112 Codec for Cyclic Code (2112,2080)
    • Small Size
    • Implements FEC Sublayer for 10GBASE-R (section 74 of the IEEE 802.3 standard)
    • 10G/40G/100G Ethernet MAC-friendly interface
    • Practically self-contained: requires only memory for one 2112-bit block in the decoder.
    Block Diagram -- 66/2112 Codec for Cyclic Code (2112,2080)
  • DVB-GSE Encapsulator and Decapsulator
    • Compliant with ETSI TS 102 606-1 V1.2.1 (Annex D, DVB-GSE Lite)
    • Support for multi-protocol encapsulation (IPv4, IPv6, MPEG, Ethernet, etc.)
    Block Diagram -- DVB-GSE Encapsulator and Decapsulator
  • BCH Encoder/Decoder
    • BCH decoder compliant with the DVB-T2/S2 standard.
    • Available for Altera/Xilinx FPGA or ASIC implementation.
    • High speed design.
    • BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
    Block Diagram -- BCH Encoder/Decoder
  • DVB-RCS2 Multi-Carrier Receiver
    • Compliant with ETSI EN 301 545-2 (DVB-RCS2)
    • Support for Linear Modulation Bursts of Table A-1
    • Optional support for Spread-spectrum
    Block Diagram -- DVB-RCS2 Multi-Carrier Receiver
  • DVB-S2X Wideband LDPC/ BCH Decoder
    • Compliant with DVB-S2 and DVB-S2X
    • Support for decoding of BBFRAMEs
    • Support for ACM, CCM, and VCM
    Block Diagram -- DVB-S2X Wideband LDPC/ BCH Decoder
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