Reducing power in AMD processor core with RTL clock gating analysis

Steve Kommrusch - AMD, Inc.
EETimes (2/4/2013 10:45 AM EST)

Lowering the power consumption of consumer products and networking centers is an important design consideration, and this effort begins with many of the chips that go into these devices. Semiconductor design innovators like AMD want to improve on  previous generation designs in terms of faster performance in a given power envelope, higher frequency at a given voltage, and improved power efficiency through clock gating and unit redesign.

With these aims, the AMD low-power core design team used a power analysis solution that helped analyze pre-synthesis RTL clock-gating quality, find opportunities for improvements, and generate reports that the engineering team could use to decrease the operating power of the design. By targeting pre-synthesis RTL, power analysis can be run more often and over a larger number of simulation cycles — more quickly and with fewer machine resources than tools that rely on synthesized gates. The focus on clock gating and the quick turnaround of RTL analysis allowed AMD to achieve measurable power reductions for typical applications of a new, low-power X86 AMD core.

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