NoC Interconnect Improves SoC Economics

Initial Investment is Low Compared to SoC Performance and Cost Benefits

by Objective Analysis

As systems on chip (SoCs) have grown in complexity and cost, one of the more critical factors for an SoC’s economic success in the marketplace has become its interconnect.

The interconnect has a significant impact on SoC costs because it influences four key factors of SoC design: die size, power consumption, design time, and performance.

• Die size can increase if conventional interconnect routing wire and gate area requirements explode due to the increasing number of IP blocks in a SoC.
• Power consumption can mushroom if an SoC’s interconnect cannot easily be configured for advanced power management schemes like dynamic frequency and voltage scaling (DVFS).
• Project design time can extend if the SoC’s interconnect becomes difficult to configure and verify. This can slow downstream designs if a platform-based design methodology is used as a basis for derivative SoC designs.
• Performance can suffer if an interconnect approach cannot adapt to changing requirements over the SoC’s design cycle and product life for changing SoC IP blocks, QoS, bandwidth, latency, security and clock frequency.

As the one piece of IP that touches all other functional IP blocks in an SoC, the interconnect, along with its configuration, verification, and utility, is the critical path to ensuring the proper operation of a modern SoC.

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