Picking the right built-in self-test strategy for your embedded ASIC
Sunit Bansal and Sumeet Aggarwal
8/2/2010 6:29 PM EDT
Test time is a significant component of ASIC cost. It needs to be minimized and yet has to have maximum coverage to ensure zero-defect scenario for an automotive application. Such test modes usually accompany memory built-in self test (MBIST) mode, which goes through all the bit-cells for all memory banks in a design.
Depending on the implementation of BIST module (Figure 1, below), we may have parallel and serial access capabilities to test the same. This test is performed at wafer level and package level. We usually have multiple packages available for SoC, which has a different number of power pads available.
To read the full article, click here
Related Semiconductor IP
- Temperature Glitch Detector
- Clock Attack Monitor
- SoC Security Platform / Hardware Root of Trust
- SPI to AHB-Lite Bridge
- Octal SPI Master/Slave Controller
Related White Papers
- FPGA to ASIC Strategy for Communication SoC Designs
- Choosing an effective embedded SoC ASIC design strategy
- Self-testing in embedded systems: Software failure
- Test engineers must join ASIC flow early