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DDR2 Controller IP

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Compare 28 DDR2 Controller IP from 10 vendors (1 - 10)
  • DDR2 Monitor Verification IP
    • Supports DDR2 memory devices from all leading vendors
    • Quickly validates the implementation of the DDR2 standard
    • Constantly monitors DDR2 behavior during simulation
    • Checks for following
    Block Diagram -- DDR2 Monitor Verification IP
  • QDR2 Synthesizable Transactor
    • Supports 100% of QDR2 protocol standard CY7C1314CV18
    • Supports separate independent read and write data ports with concurrent read and write operation
    • Supports full data coherency, providing most current data
    • Supports synchronous pipeline read with self-timed late write
    Block Diagram -- QDR2 Synthesizable Transactor
  • GDDR2 Synthesizable Transactor
    • Supports 100% of GDDR2 protocol standard
    • Supports all the GDDR2 commands as per the specs
    • Supports all types of timing and protocol violation detection
    • Supports all mode registers programming
    Block Diagram -- GDDR2 Synthesizable Transactor
  • DDR2 Synthesizable Transactor
    • Supports 100% of DDR2 protocol standard JESD79-2F
    • Supports all the DDR2 commands as per the specs
    • Supports double data rate interface
    • Supports up to 4 GB device density
    Block Diagram -- DDR2 Synthesizable Transactor
  • DDR2 DFI Verification IP
    • Compliant with DFI version 2.0 or higher Specification.
    • DFI-DDR2 Applies to :
    • DDR2 protocol standard JESD79-2F Specification
    • Supports all Interface Groups.
    Block Diagram -- DDR2 DFI Verification IP
  • DDR2 Memory Model
    • Supports DDR2 memory devices from all leading vendors.
    • Supports 100% of DDR2 protocol standard JESD79-2F.
    • Supports all the DDR2 commands as per the specs.
    • Supports double data rate interface.
    Block Diagram -- DDR2 Memory Model
  • DDR2 DFI Assertion IP
    • Specification Compliance
    • Compliant with DFI version 2.0 or higher Specification.
    • DFI-DDR2 Applies to :
    • DDR2 protocol standard JESD79-2F Specification
    Block Diagram -- DDR2 DFI Assertion IP
  • DDR2 Assertion IP
    • Specification Compliance
    • Compliant with DDR2 specifications.
    • Supports all DDR2 data widths and address widths.
    • Supports all DDR2 bank address widths.
    Block Diagram -- DDR2 Assertion IP
  • DDR Assertion IP
    • Specification Compliance
    • Quickly validates the implementation of the DDR standard
    • Checks for following
    • Check-points include power on, Initialization and power off rules,
    Block Diagram -- DDR Assertion IP
  • DDR2 Controller IIP
    • Supports DDR2 protocol standard JESD79-2F Specification.
    • Compliant with DFI-version 2.0 or higher Specification.
    • Supports all the DDR2 commands as per the specs.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    Block Diagram -- DDR2 Controller IIP
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