MIPI M-PHY IP for UMC
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MIPI M-PHY IP
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15
MIPI M-PHY IP
for UMC
from 6 vendors
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10)
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MIPI M-PHY v4.1 IP, Silicon Proven in UMC 28 HPC
- Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
- Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
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MIPI M-PHY v3.1 IP, Silicon Proven in UMC 40LP
- Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
- Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
- Support LS-MODE PWM-G1 to PWM-G5 with data rate up to 144Mb/s
- Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec.
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MIPI M-PHY Compliant (HS-G2) IP
- Complies with MIPI Standard for M-PHY, Draft Specification v0.90.
- Dual-simplex point-to-point interface with ultra low voltage differential signaling
- Slew-rate control for EMI reduction
- Supports all HS modes (GEAR 1-2)
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MIPI M-PHY v3.1 IP in TSMC(12/16nm, 28nm, 40nm, and 55nm)
- Supports RMMI interface for applications such as UNIPRO protocol (UFS, CSI-3, DSI-2) and DigRF
- High speed gears, HS-G1A/B, HS-G2A/B and HS-G3A/B with scalable power consumptions
- Burst mode CDR with short sync length (< 16SI)
- Low speed PWM Gears from G1 to G4 with ultra-low power consumptions
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MIPI M-PHY - UMC 40nm
- Compliant to MIPI Alliance Standard for M-PHY specification Version 3.0
- Supports high speed data transfer G1A/B, G2A/B and G3A/B with data rates of up to 5830.4 Mbps
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MIPI M-PHY TX/RX + Controller
- Compliant with MIPI Alliance Standard for MIPI M-PHY V4.1 Specifications
- Supports standard RMMI interface compliant to M-PHY Specifications
- Supports HS Mode (GEAR1~4, A/B)
- Supports data rate up to 11.6608Gbps per lane