INNOSILICON M-PHY implements MIPI M-PHY protocol V4.1. The M-PHY protocol specification is a part of group of communication protocols defined by MIPI Alliance standards intended for mobile system chip to chip communications. The M-PHY specification is specifically targeted to be suitable for multiple protocols, and for a wide range of applications.
INNOSILICON M-PHY includes transmitters and receivers to implement full-duplex operations. The IP supports multiple BURST modes, including HS, LS for improved power efficiency, and multiple power saving modes where power consumption can be traded-off against recovery time. The INNOSILICON I/O and ESD are also built- in, providing a convenient, drop- in PHY. The design is optimized for high speed applications with robust timing and small silicon area.
The INNOSILICON M-PHY supports the electrical portion of MIPI M -PHY V4.1 standard and cost-effectively adds MIPI M-PHY V4.1 capability to any SOC.
MIPI M-PHY TX/RX + Controller
Overview
Key Features
- Compliant with MIPI Alliance Standard for MIPI M-PHY V4.1 Specifications
- Supports standard RMMI interface compliant to M-PHY Specifications
- Supports HS Mode (GEAR1~4, A/B)
- Supports data rate up to 11.6608Gbps per lane
- Supports M-PHY Type-I (PWM-G1~7)
- Supports M-PHY Type-II
- Supports reference clocks frequency: 19.2/26/38.4/52 MHz
- Supports LS-BURST, HS-BURST, STALL, SLEEP, HIBERN8 states
- Dynamic configuration and control via core ports
- Supports 10/20/40-bit width symbol bus
- Supports PRBS9/CUSTOM/CRPAT/CJTPAT pattern in test mode
- Supports Near-end BIST and Far-end loopback
- Supports CSI-3SM, LLI, and SSIC IP
- Support slew-rate control for reducing EMI
Deliverables
- Databook and physical implementation guides Netlist (Spice format for LVS)
- Library Exchange Format (LEF)
- Verilog Models
- GDSII to Foundry IP Merge
- Module integration guidelines
- Silicon validation report (when available)
- Evaluation board (when available)
Technical Specifications
Foundry, Node
Samsung 14/5nm, TSMC 55/40/28/22/16/12/6nm, GF 55/28/22/14/12nm, SMIC 55/40/28/14nm, UMC 55/40/28/22nm, HLMC 40/28nm
GLOBALFOUNDRIES
In Production:
12nm
,
14nm
LPP
,
22nm
FDX
,
28nm
SLP
,
55nm
LPX
Silicon Proven: 12nm , 14nm LPP , 22nm FDX , 28nm SLP , 55nm LPX
Silicon Proven: 12nm , 14nm LPP , 22nm FDX , 28nm SLP , 55nm LPX
SMIC
In Production:
14nm
,
28nm
HKC+
,
40nm
LL
,
55nm
LL
Silicon Proven: 14nm , 28nm HKC+ , 40nm LL , 55nm LL
Silicon Proven: 14nm , 28nm HKC+ , 40nm LL , 55nm LL
Samsung
In Production:
5nm
,
14nm
Silicon Proven: 5nm , 14nm
Silicon Proven: 5nm , 14nm
TSMC
In Production:
6nm
,
12nm
,
16nm
,
22nm
,
28nm
HPC
,
28nm
HPCP
,
28nm
HPM
,
40nm
G
,
40nm
LP
,
55nm
LP
Silicon Proven: 6nm , 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP , 55nm LP
Silicon Proven: 6nm , 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP , 55nm LP
UMC
In Production:
22nm
,
28nm
HPC
,
40nm
LP
,
55nm
Silicon Proven: 22nm , 28nm HPC , 40nm LP , 55nm
Silicon Proven: 22nm , 28nm HPC , 40nm LP , 55nm