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HDMI IP for UMC

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Compare 14 HDMI IP for UMC from 5 vendors (1 - 10)
  • HDMI 2.0 TX PHY 6Gbps in UMC 28HPC 1.8V, North/South Poly Orientation
    • Support for key HDMI 2.0 features such as 4Kx2K resolution at 60 Hz frame rate, YCbCr 4:2:0 pixel encoding format, TMDS scrambling, High Dynamic Range (HDR), CEC 2.0, and 18.0 Gbps aggregate bandwidth
    • Compliant with HDMI 2.0 and HDCP 2.3, 1.2 specification
    • Optimized for low power and small area
    • Timing hardened blocks enable simplified placement and design closure
    Block Diagram -- HDMI 2.0 TX PHY 6Gbps in UMC 28HPC 1.8V, North/South Poly Orientation
  • HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in UMC 65/55ULP
    • HDMI version 1.4 compliant transmitter
    • Supports DTV from 480i to 1080i/p HD resolution
    • Supports 24bit, 30bit and 36bit color depth per pixel
    • Integrated cable terminator
    Block Diagram -- HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in UMC 65/55ULP
  • HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP
    • HDMI version 1.4 compliant transmitter
    • Supports DTV from 480i to 1080i/p HD resolution
    • Supports 24bit, 30bit and 36bit color depth per pixel
    • Integrated cable terminator
    Block Diagram -- HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP
  • HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in UMC 28HPC
    • HDMI version 1.4 compliant transmitter
    • Supports DTV from 480i to 1080i/p HD resolution
    • Supports 24bit, 30bit and 36bit color depth per pixel
    • Integrated cable terminator
    Block Diagram -- HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in UMC 28HPC
  • HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in UMC 65/55ULP
    • HDMI version 1.4 compliant receiver
    • Supports DTV from 480i to 1080i/p HD resolution
    • Supports 24bit, 30bit and 36bit color depth per pixel
    • HDMI version 1.4a, HDCP revision 1.3 and DVI version 1.0 compliant receiver
    Block Diagram -- HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in UMC 65/55ULP
  • HDMI 1.4 Transmitter IP in UMC 40LP
    • - Clock range : 25-300MHz
    • - Built in Band Gap Reference (BGR), PLL, Serializer
    • - PADS cell includes ESD protection circuit
    • - Built in termination resistor
  • HDMI2.0 TX PHY
    • Area: 0.604mm2 (592um x 1020um) including IO and ESD
    • Note: The area parameters are for reference only. Please refer to the final LEF file for the actual values.
    • Compliant with HDMI2.0, HDMI1.4 and DVI1.0 specifications
    • Up to 6Gbps per data channel
  • HDMI2.0/1.4 TX PHY & Controller
    • Compliant with HDMI2.0, HDMI1.4 and DVI1.0 specifications
    • Up to 6Gbps per data channel
    • Typical 24MHz or 27MHz reference clock
    • Supports YUV4:4:4, YUV4:2:2, YUV4:2:0 and RGB4:4:4 video formats
  • HDMI2.0 Receiver PHY & Controller
    • Area: 0.92mm2 including IO and ESD for PHY and 0.78mm2 for Controller without memory
    • Compliant with HDMI2.0, HDMI1.4 and DVI1.0 specification
    • Typical 24Mhz reference clock
    • Support YUV4:4:4, YUV4:2:2, YUV4:2:0 and RGB4:4:4 video format
  • HDMI2.0 Receiver PHY
    • Area: 2.1mm2 (1200um x 1750um) including IO and ESD
    • Compliant with HDMI2.0, 1.4 and DVI1.0 specifications
    • Support clock input up to 340MHz
    • Support data input up to 6Gbps per data channel
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