HDMI2.0/1.4 TX PHY & Controller

Overview

Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI2.0, HDMI1.4, and DVI 1.0 specifications. The video resolution supports up to 2160P@60Hz.
Innosilicon HDMI TX IP consists of a digital controller and a physical layer.
? The digital controller receives video, audio, synchronous signals, and control signals from the SoC logic and outputs encoded data to the physical layer.
? The physical layer contains 1 clock channel and 3 data channels, PLL, and bias circuit. The clock channel transmits clock signals up to 340MHz to a receiver. Each data channel consists of a serializer and a driver. The serializer converts the parallel input data to 1-bit high speed serial stream and the driver converts the digital serial data to low swing differential signals with typical DC-coupled connection. The data rate is up to 6Gbps per channel. PLL generates the clocks required by data channels and the digital logic. The bias circuit generates voltage and current reference.
Innosilicon HDMI TX IP offers reliable implementation for HDMI interface, which can be integrated in the SoC used in multimedia devices.

Key Features

Compliant with HDMI2.0, HDMI1.4 and DVI1.0 specifications
Up to 6Gbps per data channel
Typical 24MHz or 27MHz reference clock
Supports YUV4:4:4, YUV4:2:2, YUV4:2:0 and RGB4:4:4 video formats
Supports 8/10/12-bit color depth
Supports 8-channel I2S or 2-channel S/PDIF interface for audio input
Supports audio sampling rate up to 192kHz
Supports standard I2C master interface for DDC interface
Supports programmable output swing, termination, and pre-emphasis
Supports display resolution up to 2160P/60Hz
Supports BIST logic
Supports APB interface for internal register access
Built-in low jitter PLL and bandgap reference

Benefits

Very Low power
Small Area, easy to integrate
Test chip and test board available
FPGA integration support available

Deliverables

Databook and detailed physical implementation guides for the complete PHY
Library Exchange Format (LEF) file with pin size and locations
Gate-level netlist and Standard Delay Format (SDF) Timing file
Layout Versus Schematic (LVS) flattened netlist in spice format and report
Encrypted Verilog Models
GDSII database for foundry merge
Module integration guidelines
Silicon validation report (when available)
Evaluation board (when available)

Technical Specifications

Foundry, Node

HLMC 28nm, SMIC 40/28/14nm, UMC 40nm, TSMC 28/22/16/12/6nm, Samsung 14/10/8nm, GF 28/22/14/12nm

GLOBALFOUNDRIES

In Production: 12nm , 14nm LPP , 22nm FDX , 28nm SLP
Silicon Proven: 12nm , 14nm LPP , 22nm FDX , 28nm SLP

SMIC

In Production: 14nm , 28nm HKC+ , 40nm LL
Silicon Proven: 14nm , 28nm HKC+ , 40nm LL

Samsung

In Production: 8nm , 10nm , 14nm
Silicon Proven: 8nm , 10nm , 14nm

TSMC

In Production: 6nm , 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM
Silicon Proven: 6nm , 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM

UMC

In Production: 40nm
Silicon Proven: 40nm

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