Crypto Accelerator IP for TSMC

Welcome to the ultimate Crypto Accelerator IP for TSMC hub! Explore our vast directory of Crypto Accelerator IP for TSMC
All offers in Crypto Accelerator IP for TSMC
Filter
Filter

Login required.

Sign in

Compare 35 Crypto Accelerator IP for TSMC from 7 vendors (1 - 10)
  • True Random Number Generator
    • Patented test circuits on the oscillators to detect lockingto periodic signals.
    • Repeating output data detection on NRBG and DRBG (compliant with [FIPS 140-2]).
    • Hardware implemented ‘Repetition Count’ and ‘Adaptive Proportion’ tests on the Noise Source (compliant with [SP 800-90B]).
    • Continuous tests on the Noise Source (compliant with [AIS-31]): ‘monobit test’, ‘poker test’, ‘runs test’, ‘longruns test’ and ‘Noise Source failure’.
    Block Diagram -- True Random Number Generator
  • Quantum-Driven Hardware Root-of-Trust - Physical Unclonable Function (PUF)
    • Scalability unlocked
    • Secure root-of-trust
    • No key injection
    Block Diagram -- Quantum-Driven Hardware Root-of-Trust - Physical Unclonable Function (PUF)
  • TESIC RISC-V CC EAL5+ Secure Element Soft/Hard Macro
    • CC EAL5+ secure microcontroller system
    • CC EAL5+ secure cryptography
    • CC EAL5+ security sensors
    Block Diagram -- TESIC RISC-V CC EAL5+ Secure Element Soft/Hard Macro
  • TESIC CC EAL5+ Secure Element IP Core
    • CC EAL5+ secure microcontroller system
    • CC EAL5+ secure cryptography
    • CC EAL5+ security sensors
    Block Diagram -- TESIC CC EAL5+ Secure Element IP Core
  • NIST FIPS-197 Compliant Ultra-Low Power AES IP Core
    • Compliant to Advanced Encryption Standard (AES) (FIPS PUB 197).
    • Supports both encryption and decryption functions.
    • Supports 128/192/256-bit Cipher keys.
    • Processes an 128-bit block in 480/582/684 clock cycles for 128/192/256-bits cipher keys respectively.
    Block Diagram -- NIST FIPS-197  Compliant Ultra-Low Power AES IP Core
  • 802.11i CCMP/TKIP IP Core
    • Small size:
    • Includes key lookup, encryption, decryption, header parsing and modification, key expansion and data interface
    • Uses external memory for key storage;
    • Configurable number of keys supported; 64 bytes are required per bidirectional link
    Block Diagram -- 802.11i CCMP/TKIP IP Core
  • IEEE 802.16e (WiMAX) AES Core
    • Small size: from 8,900 ASIC gates at 802.16 data speeds
    • Completely self-contained: does not require external memory
    • Includes encryption, decryption, key expansion and data interface
    • Support for Counter Mode Encryption (CTR) operation and CCM extensions (Counter Mode with CBC MAC)
    Block Diagram -- IEEE 802.16e (WiMAX) AES Core
  • 802.15.3 CCM AES Core
    • Small size: From 9,500 ASIC gates at 802.15.3 data Speeds.
    • High data rate: up to 8 Gbps for IEEE 802.15.3c / ECMA-387 (TC 48) / IEEE 802.11ad 60 GHz PHY
    • Completely self-contained: does not require external memory
    • Includes encryption, decryption, key expansion and data interface
    Block Diagram -- 802.15.3 CCM AES Core
  • Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core
    • Encrypts using the AES Rijndael Block Cipher Algorithm.
    • Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST). FIPS-197 validated (AESAVS).
    • Processes 128-bit data blocks with 8, 16 or 32-bit data interface
    • Employs key sizes of 128 bits (AES128), 192, or 256 bits (AES256)
    Block Diagram -- Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core
  • 802.11i CCM (CTR+CBC) AES Core for WiFi WLAN
    • 8,900 ASIC gates at 802.11a/g OFDM data speeds
    • Completely self-contained: does not require external memory
    • Includes encryption, decryption, key expansion and data interface
    • Support for Counter Mode Encryption (CTR) operation and CCM extensions (Counter Mode with CBC MAC, AES0CTR per NIST SP800-38C)
    Block Diagram -- 802.11i CCM (CTR+CBC) AES Core for WiFi WLAN
×
Semiconductor IP