The EIP-53 Poly engine is an efficient hardware implementation of the Poly1305 algorithm, as specified by the Internet Research Task Force (IRTF), RFC7539 standard, and for use in TLS1.3(Draft). The accelerator includes I/O registers and a Poly1305 HASH core.
Designed for fast integration, low gate count, and maximum performance, the Poly1305 Engine provides a reliable and cost-effective IP solution that is easy to integrate into SoC designs.
Poly1305 Crypto Accelerator
Overview
Key Features
- Pipelined high speed Wide bus interface
- R Key and S Key inputs – 128-bit wide
- Digest input – 131-bit wide
- DMA and AEAD support
- Fully synchronous design
- High speed and low gate-count configurations
- Data output – 131-bit wide
Benefits
- High-speed Poly1305 solution.
- Silicon-proven implementation.
- Fast and easy to integrate into SoCs.
- Flexible layered design.
- Complete range of configurations.
- World-class technical support
Applications
- TSL1.3
Deliverables
- Documentation
- Hardware Reference and Programmer Manual
- Integration Manual
- Verification Specification
- Synthesizable Verilog RTL source code
- Self-checking RTL test bench, including test vectors and expected result vectors
- Simulation scripts
- Configurations:
- EIP-53a
- High-speed
- 7.5 bits/clk
- 44k gates
- up to 900 MHz
- EIP-53a-buf
- High-speed
- 14.2 bits/clk
- 46.1k gates
- up to 300 MHz
- EIP-53e
- Low gate count
- 3.1 bits/clk
- 28.7k gates
- up to 700 MHz
- EIP-53e-buf
- Low gate count
- 3.8 bits/clk
- 30.4k gates
- up to 300 MHz
Technical Specifications
Foundry, Node
Any
Maturity
Silicon Proven
Availability
Now
TSMC
Silicon Proven:
7nm
,
16nm
,
28nm
,
40nm
G