IP Catalog > Foundries > SMIC > Interface IP > Interconnect IP > PCI IP

PCI IP for SMIC

Welcome to the ultimate PCI IP for SMIC hub! Explore our vast directory of PCI IP for SMIC
All offers in PCI IP for SMIC
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (23)
Compare 23 PCI IP for SMIC from 7 vendors (1 - 10)
  • PCIe 2.0 PHY, SMIC 28HKMG18 x1, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • PCIe L1 substate power management
    • Supports power gating and power island
    Block Diagram -- PCIe 2.0 PHY, SMIC 28HKMG18 x1, North/South (vertical) poly orientation
  • PCIe 3.1 Controller with AXI
    • Compliant with the PCI Express 3.1/3.0, and PIPE (16- and 32-bit) specifications
    • Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
    • Supports Endpoint, Root-Port, Dual-mode configurations
    • Supports x16, x8, x4, x2, x1 at 8 GT/s, 5 GT/s, 2.5 GT/s speeds
    • Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
    • Supports many ECNs including LTR, L1 PM substates, etc.
    Block Diagram -- PCIe 3.1 Controller with AXI
  • PCIe 2.0 PHY in SMIC (40nm, 28nm)
    • Physical coding sublayer (PCS) block with PIPE interface
    • Supports PCIe power management features, including L1 substate
    • Power gating for lowest standby power
    • Low active power using voltage mode TX with under drive supply options
  • PCIe4/3/2/1 PHY & Controller
    • Reference Clock:
    • Internal PLL:
    • Data Transmit:
    • Data Receive:
  • SGMII PHY
    • General:
    • Interface:
    • PMA-TX:
    • PMA-RX:
  • PCIe5.0 PHY & Controller
    • Fully compliant with PCI Express Base Specification Revision 5.0
    • Fully compliant with PIPE Specifications Revision 4.4.1
    • Support Root Complex and Endpoint Mode
    • Support Gen1 (2.5Gbps), Gen2 (5Gbps), Gen3 (8Gbps), Gen4 (16Gbps), Gen5 (32Gbps)
  • PCIe4.0 PHY
    • Reference Clock:
    • Internal PLL:
    • Data Transmit:
    • Data Receive:
  • PCIe4.0 Controller
    • Fully compliant with PCI Express Base Specification Revision 4.0.
    • Fully compliant with PIPE Specifications Revision 4.4.1.
    • Support Root Complex and Endpoint Mode.
    • Support Gen1 (2.5Gbps), Gen2 (5Gbps), Gen3 (8Gbps), Gen4 (16Gbps)
  • PCIe3.0 PHY
    • Reference Clock:
    • Internal PLL:
    • Data Transmit:
    • Data Receive:
  • PCIe3.0 Controller
    • Fully compliant with PCI Express Base Specification Revision 3.0.
    • Fully compliant with PIPE Specifications Revision 4.4.1
    • Support Root Complex and Endpoint Mode.
    • Support Gen1 (2.5Gbps), Gen2 (5Gbps), Gen3 (8Gbps)
×
Semiconductor IP