PCIe4/3/2/1 PHY & Controller

Overview

The Innosilicon PCIe4.0 PHY is a highly configurable PHY capable of supporting speeds up to 16Gbps within a single lane. For this particular datasheet, the PHY has been configured to support PCIe4.0 specifically, but the PHY itself can be configured to support a wide range of HS SERDES protocols through changes to the PCS layer and register settings.
The PHY is physically configured in order to support multi-lane solutions. There is a common block with Tx PLL, reference clock input, bandgap, bias circuitry and termination calibration. This common block can then support up to 4 lanes of Tx/Rx.

Key Features

Reference Clock:

25-300MHz, integer multiple of Serial output
+/-300ppm frequency stability (<20Gbps)
+/-100ppm frequency stability (>=20Gbps)
Support both SRNS & SRIS modes
Configurable as reference clock repeater

Internal PLL:

Used to drive all PHY transmitters and receivers
LC-tank architecture operational from 16-32Gbps
Ring PLL covering 1.0-16.0Gbps
Programmable pre-divider & feedback divider
Initiative SSC or reference clock based passive SSC
LOCK indication

Data Transmit:

Rates supported from 1.0-16.0Gbps
AC coupled
50? impedance, internally calibrated
3 tap pre/post-cursor de-emphasis, programmable
200-1000mV differential peak-peak, programmable
Programmable Rise/Fall times

Data Receive:

AC coupled
50? impedance, internally calibrated
200-1200mV differential peak-peak
CTLE, programmable
DFE, 6-tap programmable
CDR

Testing:

Scan
BIST with PRBS7, PRBS23 and PRBS31(PG & SD)
Loopback (near-end, far-end, on/off-die)
On-chip scope (eye height & width)
Analog and digital probe points
HTOL
IDDQ

ESD:

HBM 2000V, [JEDEC JS-001-2014]
MM100V, [JEDEC JESD22-A115C]
CDM 250V, [JEDEC JESD22-C101F]

Latch Up:

+-200mA for IO and 1.5*Vsupply for power rails

Package:

Wire bond with careful SI/PI analysis for 8Gbps and below
Flip-Chip with careful SI/PI analysis for 8Gbps and up

Interface with controller:

PIPE4.3 & 32 bits data bus for PCIe

Benefits

Higher bandwidth upto 64Gbps in X4 mode
Support different configuration for different protocol applications
Lowest power consumption per Gbps data rates

Deliverables

Verilog Sim Behavioral simulation model for the PHY
Encrypted IO spice netlist for SI evaluation
Integration Guidelines
Test Guidelines
GDSII Layout and layer map for foundry merge
Place and Route LIB and LEF views for the AFE
LVS and DRC verification reports

Technical Specifications

Foundry, Node

TSMC 55/40/28/22/16/12/7/5/4/3nm, Samsung 28/14/10/8/4nm, SMIC 55/40/28/14nm, GF 55/28/22/14/12nm. UMC 55/40/28/22nm, HLMC 40/28nm

GLOBALFOUNDRIES

In Production: 12nm , 14nm LPP , 22nm FDX , 28nm SLP , 55nm LPX
Silicon Proven: 12nm , 14nm LPP , 22nm FDX , 28nm SLP , 55nm LPX

SMIC

In Production: 14nm , 28nm HKC+ , 40nm LL , 55nm LL
Silicon Proven: 14nm , 28nm HKC+ , 40nm LL , 55nm LL

Samsung

In Production: 4nm , 8nm , 10nm , 14nm , 28nm FDS , 28nm LPP
Silicon Proven: 4nm , 8nm , 10nm , 14nm , 28nm FDS , 28nm LPP

TSMC

In Production: 3nm , 4nm , 5nm , 7nm , 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP , 55nm LP
Silicon Proven: 3nm , 4nm , 5nm , 7nm , 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP , 55nm LP

UMC

In Production: 22nm , 28nm HPC , 40nm LP , 55nm
Silicon Proven: 22nm , 28nm HPC , 40nm LP , 55nm

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