The Innosilicon PCIE3.0 PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface for PCIE3.0 Super-Speed standard from Intel. The PHY supports PCIE3.0(8Gb/s/5Gb/s/2.5Gb/s) physical layer specifications.
The PHY module includes a top level wrapper integrating both the Physical Media Attachment (PMA) layer, and the Physical Coding Sub-Block (PCS) layer.
PCIe 3.0/3.1/USB3.0/SATA3 Combo PHY
Overview
Key Features
- Standard PHY interface enables multiple IP sources for PCI Express Logical Layer and provides a target interface for PCI Express PHY vendors.
- Supports 2.5Gb/s only or 2.5Gb/s,5.0Gb/s and 8.0Gb/s serial data transmission rate
- Utilizes 8-bit, 16-bit or 32- bit parallel interface to transmit and receive PCI Express data
- Allows integration of high speed components into a single functional block as seen by the endpoint device designer.
- Data and clock recovery from serial stream on the PCI Express bus
- Holding registers to stage transmit and receive data
- Supports direct disparity control for use in transmitting compliance pattern
- 8b/10b encode/decode and error indication
- 128b/130b encode/decode and error indication
- Receiver detection
- Beacon transmission and reception
- Selectable Tx Margining, Tx De-emphasis and signal swing values
- Receive Equalization training
Benefits
- As with all Innosilicon IP, the focus is on silicon proven, fully certified solutions providing:
- Small size
- Low power
- High ATE coverage
- Simple integration
- Flexible customization
Applications
- PCIE Card
- Solid State Disk
Technical Specifications
Foundry, Node
TSMC 40/28/22/16/12/7/5/4nm, Samsung 14/10/8nm, GF 28/22/14/12nm, SMIC 40/28/14nm, UMC 28/22nm, HLMC 40/28nm
Maturity
Silicon Proven
Availability
now
GLOBALFOUNDRIES
In Production:
12nm
,
14nm
LPP
,
22nm
FDX
,
28nm
SLP
Pre-Silicon: 28nm SLP
Silicon Proven: 12nm , 14nm LPP , 22nm FDX , 28nm SLP
Pre-Silicon: 28nm SLP
Silicon Proven: 12nm , 14nm LPP , 22nm FDX , 28nm SLP
SMIC
In Production:
14nm
,
28nm
HKC+
,
40nm
LL
Silicon Proven: 14nm , 28nm HKC+ , 40nm LL
Silicon Proven: 14nm , 28nm HKC+ , 40nm LL
Samsung
In Production:
8nm
,
10nm
,
14nm
Silicon Proven: 8nm , 10nm , 14nm
Silicon Proven: 8nm , 10nm , 14nm
TSMC
In Production:
4nm
,
5nm
,
7nm
,
12nm
,
16nm
,
22nm
,
28nm
HPC
,
28nm
HPCP
,
28nm
HPM
,
40nm
G
,
40nm
LP
Silicon Proven: 4nm , 5nm , 7nm , 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP
Silicon Proven: 4nm , 5nm , 7nm , 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP
UMC
In Production:
22nm
,
28nm
HPC
Silicon Proven: 22nm , 28nm HPC
Silicon Proven: 22nm , 28nm HPC
Related IPs
- PCIe Gen5/CXL combo PHY, x2-lane, RC/EP, TSMC 12FFC, N/S orientation
- High-Performance Lossless Compression/Encryption Combo Core
- DDR2/DDR3/DDR3L/LPDDR/LPDDR2/LPDDR3 6 in one combo IO with auto calibration - 40nm LL
- MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+
- MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) IP in TSMC 65LP
- HDMI - Display Port Combo PHY IP, Silicon Proven in TSMC 28HPC+