PCIe3.0 PHY

Overview

The Innosilicon PCIe3.0 PHY is a highly configurable PHY capable of supporting speeds up to 8Gbps within a single lane. For this particular datasheet, the PHY has been configured to support PCIe3.0 specifically, but the PHY itself can be configured to support a wide range of HS SERDES protocols through changes to the PCS layer and register settings.
The PHY is physically configured in order to support multi-lane solutions. There is a common block with Tx PLL, reference clock input, bandgap, bias circuitry and termination calibration. This common block can then support up to 4 lanes of Tx/Rx.

Key Features

Reference Clock:

25-300MHz, integer multiple of Serial output
+/-300ppm frequency stability (<20Gbps)
Support both SRNS & SRIS modes
Configurable as reference clock repeater

Internal PLL:

Used to drive all PHY transmitters and receivers
Ring PLL covering 1.0-8.0Gbps
Programmable pre-divider & feedback divider
Initiative SSC or reference clock based passive SSC
LOCK indication

Data Transmit:

Rates supported from 1.0-8.0Gbps
AC coupled
50? impedance, internally calibrated
3 tap pre/post-cursor de-emphasis, programmable
200-1000mV differential peak-peak, programmable
Programmable Rise/Fall times

Data Receive:

AC coupled
50? impedance, internally calibrated
200-1200mV differential peak-peak
CTLE, programmable
DFE, 6-tap programmable
CDR

Testing:

Scan
BIST with PRBS7, PRBS23 and PRBS31(PG & SD)
Loopback (near-end, far-end, on/off-die)
On-chip scope (eye height & width)
Analog and digital probe points
HTOL
IDDQ

ESD:

HBM 2000V, [JEDEC JS-001-2014]
MM100V, [JEDEC JESD22-A115C]
CDM 250V, [JEDEC JESD22-C101F]

Latch Up:

+-200mA for IO and 1.5*Vsupply for power rails

Package:

Wire bond with careful SI/PI analysis for 8Gbps and below
Flip-Chip with careful SI/PI analysis for 8Gbps and up

Interface with controller:

PIPE4.3 & 32 bits data bus for PCIe and USB3.x

Benefits

Standard PHY interface enables multiple IP sources for PCI Express Logical Layer and provides a target interface for PCI Express PHY vendors.
Supports 2.5/5.0Gb/s serial data transmission rate
Utilizes a 16-bit or 32-bit interface to transmit and receive PCI Express data
Allows integration of high speed components into a single functional block.
Data and clock recovery from serial stream on the PCI Express bus
Holding registers to stage transmit and receive data
Supports direct disparity control for use in transmitting compliance pattern
8b/10b encode/decode and error indication
Receiver detection
Beacon transmission and reception
Selectable Tx Margining, FFE and signal swing values
Built in self-test and loopback test
Selectable Tx Margining and FFE taps
Selectable Rx CTLE peaking range and DFE taps
Auto calibrated and tunable on die termination (ODT)
Integrated IO with ESD protection aimed at HBM 2KV, MM 100V and CDM 250V
Well-tuned T-coil to promote ultra-high bandwidth

Deliverables

Verilog Sim Behavioral simulation model for the PHY
Encrypted IO spice netlist for SI evaluation
Integration Guidelines
Test Guidelines
GDSII Layout and layer map for foundry merge
Place and Route LIB and LEF views for the AFE
LVS and DRC verification reports

Technical Specifications

Foundry, Node

SMIC 40nm, TSMC 22nm

SMIC

In Production: 28nm
Silicon Proven: 28nm

TSMC

In Production: 22nm
Silicon Proven: 22nm

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