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Interconnect IP for SMIC

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Compare 178 Interconnect IP for SMIC from 17 vendors (1 - 10)
  • PCIe 3.1 Controller with AXI
    • Compliant with the PCI Express 3.1/3.0, and PIPE (16- and 32-bit) specifications
    • Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
    • Supports Endpoint, Root-Port, Dual-mode configurations
    • Supports x16, x8, x4, x2, x1 at 8 GT/s, 5 GT/s, 2.5 GT/s speeds
    • Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
    • Supports many ECNs including LTR, L1 PM substates, etc.
    Block Diagram -- PCIe 3.1 Controller with AXI
  • I2C Controller IP – Master, Parameterized FIFO, AXI Bus
    • The DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0 AXI System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
    • The DB-I2C-M-AXI is a Master I2C Controller that controls the Transmit or Receive of data to or from slave I2C devices. Figure 1 depicts the system view of the DB-I2C-M AXI Controller IP Core embedded within an integrated circuit device.
    Block Diagram -- I2C Controller IP – Master, Parameterized FIFO, AXI Bus
  • I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus

    • The DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AMBA AHB Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).

      The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.

      The DB-I2C-MS-AHB is a Master / Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.

    Block Diagram -- I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus
  • I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus

    • The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).

      The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.

      The DB-I2C-MS-APB is a Master/Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.

    Block Diagram -- I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus
  • I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
    • The DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AMBA AXI Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).
    • The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
    • The DB-I2C-MS-AXI is a Master / Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.
    Block Diagram -- I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
  • Complete USB Type-C Power Delivery IP
    • Mixed signal Analog Front End Macros for 65n, 130n, 150nm, and 180n technologies.
    • RTL code from AFE to I2C compatible register set.
    • Stand alone C code for Protocol, Device Policy Manager, and System Policy Manager.
    • IP demonstration & development board, with compliance reports. 
    • Full chip integration of USB Type-C, and associated software.
    Block Diagram -- Complete USB Type-C Power Delivery IP
  • USB 2.0 femtoPHY - SMIC 28PS18 x1, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - SMIC 28PS18 x1, North/South (vertical) poly orientation
  • USB 2.0 femtoPHY - SMIC 28HKMG18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - SMIC 28HKMG18 x1, OTG, North/South (vertical) poly orientation
  • PCIe 2.0 PHY, SMIC 28HKMG18 x1, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • PCIe L1 substate power management
    • Supports power gating and power island
    Block Diagram -- PCIe 2.0 PHY, SMIC 28HKMG18 x1, North/South (vertical) poly orientation
  • MIPI DPHY v1.2 Tx 4 Lanes - SMIC 28PS 1.8V, North/South Poly Orientation
    • Compliant with the MIPI D-PHY specification, v1.2
    • Fully integrated hard macro
    • Up to 2.5 Gbps per lane
    • Aggregate throughput up to 10 Gbps in 4 data lanes
    Block Diagram -- MIPI DPHY v1.2 Tx 4 Lanes - SMIC 28PS 1.8V, North/South Poly Orientation
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