GDDR6X/6 Combo PHY&Controller

Overview

Innosilicon GDDR6/6X Combo IP is fully compliant to the JEDEC GDDR6/6X standard, supporting up to 16Gbps per pin for PAM2 GDDR6 and 21Gbps for PAM4 GDDR6X. The GDDR6/6X interface supports 2 channels, each with 16 bits for a total data width of 32 bits per memory device. With Speeds up to 16 Gbps/21Gbps per pin the Innosilicon GDDR6/6X PHY will offer a maximum bandwidth of up to 64 GB/s or 84GB/s per memory device. This PHY will be available in advanced FinFET nodes for leading-edge customer integration. The Innosilicon system-aware design methodology used for IP Cores delivers a customer focused experience with improved time-to-market and first-time-right quality. Innosilicon offers flexible delivery of IP cores and will work directly with the customer to provide a full system signal and power integrity analysis, creating an optimized chip layout. In the end, the customer receives a hard macro solution with a full suite of test software for quick turn-on, characterization and debug.
Innosilicon GDDR6/6X PHY DFI interface is based on DFI 5.0, and customer can license Innosilicon or third-party Memory Controller.

Key Features

Data rate up to 24Gbps for GDDR6X, 18Gbps for GDDR6
PAM4 (only for GDDR6X) and POD-135 compatible signaling
Supports both quad data rate (QDR) and double data rate (DDR) data (WCK) mode
Driver strength and on-die termination (ODT) auto calibration
Supports both Write and Read CRC
Per-bit TX and RX data phase adjustment
Internal high-performance low-jitter PLL
Supports both hardware and software training including WCK2CK training, command training, read training and write training
Dynamic eye-diagram training for Write and Read operation
TX de-emphasis EQ and RX DFE EQ to improve signal integrity
Internal VREF with DFE for data inputs, with receiver characteristics programmable per pin
Data bus inversion (DBI) and CA bus inversion (CABI)
Supports EDC full rate and half rate hold pattern, programmable EDC tracking bandwidth
Various low power modes

Benefits

World’s first silicon-proven commercial GDDR6/6X IP
Available in advanced FinFET process nodes
JEDEC JESD250 standard compliant (GDDR6)
Offers leading performance, power, and area per terabit
Optional PI/SI and thermal co-design service
Full support from IP delivery to production

Applications

Artificial intelligence
Data center, big data analytics
Crypto mining,
ADAS,
Machine learning, and deep learning.

Deliverables

Verilog models
LEF
Place-and-route abstracts
GDSII files
LVS netlists
Optional extracted HSPICE netlist for I/Os
Data book, Application notes
Silicon validation and ESD testing results
Optional PCB reference design and Package Electrical Model
Documentation: Documentation for the Innosilicon PHY will be delivered as part of the access package.

Technical Specifications

Foundry, Node

Samsung 14/12/10/8nm, SMIC 14/12nm,TSMC 28/12/7/6/5/4nm,GF14/12nm

Maturity

Silicon Proven

GLOBALFOUNDRIES

In Production: 22nm
Silicon Proven: 22nm

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