1.8V/3.3V Switchable GPIO With 3.3V I2C Open Drain & Analog in 22nm

Overview

A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation. The GPIO cell set can be configured as input, output, open-source, or open-drain with an optional internal 60K ohm pullup or pull-down resistor. Cells for IO & core power & ground with built-in ESD circuitry are included. Digital cells for 25MHz, 75MHz, and 150MHz allow optimization across SSO currents & power. A 3.3V I2C open-drain (fail-safe) and a 3.3V analog cell with ESD protection are included. The library is enriched with feed-through, filler, transition and domain-break cells to allow for flexible pad ring construction while maintaining ESD robustness. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.

Key Features

  • Multi-voltage 1.8V / 3.3V switchable operation
  • 25MHz, 75MHz, & 150MHz GPIO1 speed options
  • Full-speed output enable
  • Independent power sequencing
  • Shorted output protection
  • Schmitt trigger receiver
  • 60K? selectable pull-up or pull-down resistor
  • ESD: 2KV HBM, 500V CDM, 2KV IEC 61000-4-2

Block Diagram

1.8V/3.3V Switchable GPIO With 3.3V I2C Open Drain & Analog in 22nm Block Diagram

Deliverables

  • GDS
  • CDL netlist
  • Verilog stub
  • Verilog behavioral model
  • LEF
  • Liberty Timing Files
  • IBIS (option)
  • Electrical datasheet
  • User guide and application notes
  • Consulting and Support

Technical Specifications

Foundry, Node
22nm
Maturity
Silicon Proven, High Volume manufacturing
Availability
Immediate
TSMC
In Production: 22nm
Pre-Silicon: 22nm
Silicon Proven: 22nm
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Semiconductor IP