TSMC explains 40nm yield problems, metal-gate stacks and why 100 per cent utilisation is bad

By _Chris Edwards

July 30, 2009

With Morris Chang back in the CEO seat, it was a different kind of Taiwan Semiconductor (TSMC) that you could hear on the second quarter 2009 results conference call today. Analyst questions actually got some answers for a change, not least a hint as to which way TSMC plans to go with the high-k, metal-gate process for the future 28nm node.

The company will be taking the same route as Intel and UMC with a so-called gate-last process, not the gate-first approach favoured by IBM and the Common Platform partners. However, that answer from senior director of advanced process technologies Mark Liu did not arrive without a little prodding from his boss. It's hard to imagine former CEO - and now man in charge of finding new markets at TSMC - Rick Tsai making sure Liu answered the question.

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