TSMC on 40nm and 28nm yield issues
March 1, 2010
At the company’s executive forum held in Yokohama, Japan, TSMC’s senior vice president of R&D, Shang-yi Chiang, provided some background on why yield problems surfaced on the 40nm process — and also some indications that 28nm will not exactly be plain sailing.
Chiang pointed to the shift to immersion lithography — a choice that Intel delayed by a generation — and the use of a new low-k dielectric in the metal layers as the main culprits for the foundry’s problems. He claimed that defect density has reduced significantly since the middle of last year, when chairman Morris Chang decided to expand the team working on 40nm at TSMC.
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