Is Your Design PCIe Gen5 Ready? Verify with Synopsys VIP and Testsuite
In June 2017, PCI-SIG announced the new PCI Express 5.0 specification, at the PCI-SIG DevCon. The new version of the specification doubled bit rate to 32GT/s per lane providing about 128GB/s bandwidth for a x16 Link (16 lanes). The chart below provides a comparison of bit-rate and bandwidth for the different PCIe Generations.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related Blogs
- Check Again: Cadence Announces Release of the First PCIe 5.0 VIP - With TripleCheck!
- PCIe PIPE 4.4.1: Enabler for PCIe Gen4
- PCIe 5.0 Demos: IP and VIP for AI, Cloud, Storage, and Networking
- CCIX Over PCIe: Faster Coherent Interconnects for AI, Networking, 4G/5G, and Storage Designs
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?