SMP, Asymmetric Multiprocessing, and the HSA Foundation
When we hear the term “multiprocessing,” we often associate it with “symmetric multiprocessing (SMP).” This is because of SMP’s initial prevalence in the high-performance computing world, and now in x86/x64 servers and PCs. However, it’s been known for years that SMP’s ability to scale performance as the number of cores increases is poor.sandia IEEE SMP 300px
Processor companies serving the mobility and consumer electronics markets have avoided purely SMP solutions and instead have implemented asymmetric multiprocessing (AMP) architectures. An example of AMP is a mobile phone modem baseband SoC which contains an ARM processor and a DSP to handle control and signal processing, respectively. We also see AMP architectures in today’s mobile phone application processors, which usually have multiple CPU cores and separate discrete graphics cores, video cores, audio cores and imaging cores.
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Related Semiconductor IP
- Smart Network-on-Chip (NoC) IP
- NoC System IP
- Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
- Tessent NoC Monitor
- Network-on-Chip (NoC) Interconnect IP
Related Blogs
- Putting the "Heterogeneous" in the HSA Foundation
- Asymmetric Multiprocessing with Heterogeneous Architectures: Use the Best Core for the Job
- Symmetric Multiprocessing (SMP) RTOS on Xtensa Multicore
- ARM Cortex-A9 SMP Design Announced