PHY IP: the last frontier of configurability?
An IP announcement by LSI last week highlights several key issues in the design of a modern serial interface PHY. The block, the PHY 9500, is the fast serial interface member of a complete library of critical IP blocks for implementing mass storage controller SoCs, the TrueStore family. The PHY 9500 supports SATA 6G, SAS 6G, and Fibre Channel 4.25G interfaces from one block.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related Blogs
- How to Verify Complex PIPE Interface Based PHY Designs?
- Synopsys Accelerates Multi-Die System Designs With Successful UCIe PHY IP Tape-Out on TSMC N3E Process
- 4nm 112G-ELR SerDes PHY IP
- Enabling the Global 800G Ecosystem with 112G Ethernet PHY IP
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?