Intel's Borkar hints at future of SoC architecture and semiconductor test
November 4, 2009
In a plenary talk at the International Test Conference this morning Intel fellow Shekhar Borkar offered a tightly-reasoned description of how IC architectures will look in a few years, with some observations about the future these architectures imply for test engineers. The talk certainly represented the views of Intel's director of microprocessor technology, and may indicate the general direction of thinking within the company.
To read the full article, click here
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related Blogs
- Want to see the future of low-power SoC design? Have a look into Gary Smith’s crystal ball
- Semiconductor Assembly and Test Services (SATS) Market and Leaders
- On-chip networks: Future of SoC design
- The Future of Mobile Devices and the Semiconductor Landscape!
Latest Blogs
- Cadence Unveils the Industry’s First eUSB2V2 IP Solutions
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms