EDA Tech Forum: Deep dive in the Electronic Design Automation world
The Mentor Graphics' EDA Tech Forums at the Williams F1 Conference centre in Oxfordshire, UK provided an interesting diversity of topics I would summarize that tomorrow’s tools as well as new IP development will ensure we keep getting smarter and smarter mobile devices in our pockets without having to carry your charger!
Dr. Wally Rhines', Mentor Graphics CEO, keynote “Delivering 10X Design Improvements” made the day’s goal quite clear from the start. To achieve this tenfold increase of transistor number, we need to continuously create better methods and not only try and improve older ones. Dr. Rhines insisted that the progress made is following “The Learning Curve” and not Moore’sLaw that Gordon Moore himself revised a couple of times. At the current growth rate, Wally stated we would reach this 10X threshold in 2018 (+49% transistor/year; +13% units shipped/year) and because studies show that new tools take roughly 8 years to be widely adopted, how to tackle the 40 Billion transistor mark is being established now.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related Blogs
- Unleashing the Potential of RISC-V: A Recap of the SiFive Tech Forum
- The Top Five Takeaways from the Cybersecurity Panel at the Autonomous Tech Forum 2024
- Cadence summits Denali
- Which Direction for EDA - 2D, 3D, or 360?
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?