Design Reuse: It's Harder Than it Looks
December 7, 2009
How best can we leverage IP in an era of relentlessly increasing design complexity? That was the question on the table at this week’s IP-ESC 2009 conference here in Grenoble. I was honored to sit on a panel with Jasper Design Automation CEO Kathryn Kranen and Olivier Haller, who manages the design verification team in the Functional Verification Group at STMicroelectronics.
To read the full article, click here
Related Semiconductor IP
- Xtal Oscillator on TSMC CLN7FF
- Wide Range Programmable Integer PLL on UMC L65LL
- Wide Range Programmable Integer PLL on UMC L130EHS
- Wide Range Programmable Integer PLL on TSMC CLN90G-GT-LP
- Wide Range Programmable Integer PLL on TSMC CLN80GC
Related Blogs
- Tips on Using e Macros to Raise Abstraction and Facilitate Reuse
- Why your Internal IP Reuse Strategy is not Working
- The realities of IP reuse
- How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?