TierLogic lifts the veil: another take on the 3D FPGA
March 11, 2010
TierLogic, yet another large and expensive FPGA start-up that has been in stealth mode for years, today unveiled a radical approach to increasing the density and utility of large programmable logic devices. Like previously-announced Tabula, TierLogic describes their design as a 3D FPGA. But the two approaches are totally unlike each other, and neither is related to the concept of 3D ICs—involving stacked dice and through-silicon vias—that is currently the hot topic in SoC-of-the-future circles.
To read the full article, click here
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related Blogs
- Is the Buzz around Xilinx's 2.5D FPGA Justified?
- Altera and Micron help propel HMC, but will 3D packaging limit interest?
- Open ARM-wrestling in FPGAs
- Why FPGA startups keep failing
Latest Blogs
- Cadence Unveils the Industry’s First eUSB2V2 IP Solutions
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms