Achieve PCIe compliance and interoperability in your IP core-based design

Since its inception more than five years ago, PCIe technology has become the dominant interconnect protocol across virtually all market segments. Today, all of the major chipset vendors are implementing PCIe technology into their chipsets.

The quick adoption of PCIe technology has resulted in a market flooded with many different implementations of the PCIe specification. While, theoretically, each of these implementations should be compliant with the specification and interoperate with all other implementations, the reality is that non-compliant and non-interoperable devices do make their way to the marketplace.

When one considers the high cost of fixing a non-compliant or non-interoperable device once it reaches silicon, much less once it has been released to the market, assuring pre-silicon compliance and interoperability of a device becomes one of the most important challenges to any PCIe development process.

Recognizing this enormous cost, the EDA industry has come forth with a myriad of solutions capable of managing this obstacle. These solutions include advanced verification and assertion languages, functional coverage tools, and protocol specific models and compliance test suites.

Given the wide range of solutions made available by the EDA industry, selecting the best solution to assure pre-silicon compliance and interoperability of a device requires a thorough understanding of the issues that cause devices to be deemed noncompliant or non-interoperable.

Figure 1: If two devices are known to interoperate with a third device, then the first two should be indirectly interoperable with each other.

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