Hardware (and software) implications of Endianness in SoC design

Sandeep Yaddula, Texas Instruments
Embedded.com (March 17, 2013)

Embedded software programmers are familiar with the endianness characteristic of a computing processor. They are generally aware how, depending on endianness, different data types are stored in memory and the consequences of accessing individual byte locations of a multi-byte data element in memory.

In this article, we will review the concept of endianness from a software standpoint and will then discuss the implications of endianness for designers of hardware IP blocks and developers of device drivers when they work with a complex system such as today’s SOC.

Today’s SOCs integrate many hardware IP blocks and designers need to be aware of the order of bytes on the byte lanes of connecting buses when transferring data. In a system with several discrete hardware components such as a host processor and external devices connected to it via, say, a PCI bus, the hardware components may support different endianness modes and device driver developers need to make the data transfers among these hardware components endianness-proof.

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