Time is money! A quick fix for those pesky FPGA design errors

Angela Sutton, Synopsys
EETimes (5/4/2012 1:23 PM EDT)

In the past, preparing a first implementation of an FPGA design on the board was relatively straightforward, requiring only a single design project, a handful of source projects, and a single design engineer. Subsequent improvements to the FPGA design on the board could be reflected in a matter of hours.

Today’s designs are not so simple. FPGAs are used in production to implement complex designs such as those for consumer, computer, and communications applications, where staying ahead of the competition requires fast delivery of the next-generation system that includes new functionality or perhaps takes advantage of a new FPGA device.

And, more and more, FPGA-based prototyping systems are being used to verify huge pending ASIC designs. These types of designs typically consist of 1000s of source files and implement the equivalent of multi-million gate ASIC designs. To add to the problem, the engineer implementing and verifying the design in an FPGA may not have been the one who authored the RTL code and may therefore be unfamiliar with it.

Some FPGA systems are partitioned across multiple FPGAs, adding another level of complexity to the process.  With designs this huge and design source often foreign to the user, the time required to bring up the first working implementation of the design on the board can now be weeks, the result of a staggering number of setup requirements, ASIC design conversion issues and user errors in the overall design specification.

Users hope for quick feedback on their design specification – that is, efficient ways to identify, isolate and fix issues that prevent design completion from occurring.  The fewer design iterations needed to do this, the better. Whereas top-down implementation methodologies still work well in some cases, a hierarchical design methodology is usually more appropriate for runtime and design stability reasons.

But, that’s only one piece of the puzzle. Another important piece is the ability for the design project to proceed in the presence of errors using  synthesis “continue-on-error” technology, and then merge multiple fixes at once, incrementally, using hierarchical design approaches.  By using these methods users can find multiple errors in one design iteration and apply fixes in parallel,  potentially cutting days, if not weeks, off the time taken for initial board bring-up. Let’s explore this in more detail.

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