VESA DSC IP
Welcome to the ultimate VESA DSC IP hub! Explore our vast directory of VESA DSC IP Cores
VESA DSC IP cores provide a low-latency, low-complexity codec specifically designed for data compression over the display interface.
VESA Display Compression Codecs (DSC) IP cores can compress any image to 8 bits per pixel (bpp), which results in a 3X compression ratio for a 24 bpp image or a 3.75X compression ratio for a 30 bpp image.
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VESA DSC IP
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VESA DSC IP
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VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs
- VESA Display Stream Compression (DSC) 1.2a compliant
- Supports all DSC 1.2a mandatory and optional encoding mechanisms
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VESA DSC 1.2b Encoder for Xilinx FPGAs
- VESA Display Stream Compression (DSC) 1.2a compliant
- Supports all DSC 1.2a mandatory and optional encoding mechanisms
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VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- Complete DisplayPort™ 1.4 Receiver solution with support for VESA Display Stream Compression (DSC)
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ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
- VESA DSC 1.1 compliant
- Supports all DSC 1.1 mandatory encoding mechanisms
- Configurable maximum display resolution
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VESA DSC (Display Stream Compression) 1.2b Video Decoder
- VESA DSC 1.2 compliant
- Supports all DSC 1.2 mandatory encoding mechanisms
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VESA DSC (Display Stream Compression) 1.2b Video Encoder
- VESA DSC 1.2 compliant
- Supports all DSC 1.2 mandatory encoding mechanisms
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VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
- VESA DisplayPort 1.4 compliant
- Reed-Solomon (254,250) FEC, 10-bit symbols
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VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver
- VESA DisplayPort 1.4 compliant
- Reed-Solomon (254,250) FEC, 10-bit symbols
- Two-way interleaving for 1-, 2-, and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
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VESA Display Stream Compression (DSC) IP Core
- Supports Versions 1.1, 1.2 and 1.2a
- Supports RGB and YCbCr color spaces
- 1-to-8 slice support
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Display Stream Compression (DSC 1.2) Encoder
- VESA DSC 1.2 Compliant
- Capable of encoding up to 4K video at 30fps in FPGA and ASIC
- 8K compression available for select applications
