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V-by-One IP

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Search (26)
Compare 26 V-by-One IP from 6 vendors (1 - 10)
  • V-by-One/LVDS Tx Combo PHY, Silicon Proven in 28HPC+
    • LVDS compliant Tx
    • 4 groups of 4-Data
    • 1-Clock channels Each lane/group can be turned on/off individually Data/Clock can be assigned to any lane within the group
    • Differential polarity can be flip per lane
    Block Diagram -- V-by-One/LVDS Tx Combo PHY, Silicon Proven in 28HPC+
  • V-by-One/LVDS Rx IP, Silicon Proven in SMIC 40LL
    • LVDS compliant Rx
    • 4 groups of 4-Data, 1-Clock channels
    • Each lane/group can be turned on/off individually
    • Supports from 168Mbps to 1.5Gbps data rate
    Block Diagram -- V-by-One/LVDS Rx IP, Silicon Proven in SMIC 40LL
  • V-by-One/ LVDS Tx IP, Silicon Proven in SMIC 40LL
    • LVDS compliant Tx
    • 4 groups of 4-Data
    • 1-Clock channels Each lane/group can be turned on/off individually Data/Clock can be assigned to any lane within the group
    • Differential polarity can be flip per lane
    Block Diagram -- V-by-One/ LVDS Tx IP, Silicon Proven in SMIC 40LL
  • V-by-One/LVDS Tx IP, Silicon Proven in GF 22FDX
    • Support data rate: 0.6Gbps~4.0Gbps
    • Utilize per-lane 10bit parallel interface
    Block Diagram -- V-by-One/LVDS Tx IP, Silicon Proven in GF 22FDX
  • V-by-One/LVDS Rx IP, Silicon Proven in GF 22FDX
    • LVDS compliant Rx
    • 4 groups of 4-Data, 1-Clock channels
    • Each lane/group can be turned on/off individually
    • Supports from 168Mbps to 1.5Gbps data rate
    Block Diagram -- V-by-One/LVDS Rx IP, Silicon Proven in GF 22FDX
  • V-by-One Rx IP, Silicon Proven in SMIC 40LL
    • Wide-range data rate, up to 1Gbps, and the associated clock is DDR clock (1/2 of the data rate, up to 500MHz)
    • 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
    • DC coupling mode
    • Multi-channel shared offset
    Block Diagram -- V-by-One Rx IP, Silicon Proven in SMIC 40LL
  • V-by-One 1.4 Receiver
    • Compliant with V-by-One 1.4 specification
    • Support for up to 4 channels, with up to 4 Gbps data rate per channel
    • CDR support to resolve skew problems between clock and data in conventional transfer systems
    • Supports up to 40-bit Deep-Color in RGB/YCbCCr/RGBW/RGB/Y format Digital Video Output with selectable edge clocking
    Block Diagram -- V-by-One 1.4 Receiver
  • V-by-One 1.4 Transmitter
    • Compliant with V-by-One 1.4 specification
    • Support for up to 8 channels, with up to 4 Gbps data rate per channel
    • Supports up to 40-bit Deep-Color in RGB/YCbCCr/RGBW/RGB/Y format Digital Video Output with selectable edge clocking
    • Supports scrambling and 8b/10b encoding
    Block Diagram -- V-by-One 1.4 Transmitter
  • V-By-One PHY & Controller (Tx+ Rx)
    • Area: 1.224mm2 (1440um x 850um) including IO and ESD
    • Compliant with V-By-One HS 1.4 standard
    • Support 1/2/4/8-lane configuration
    • Support 3/4/5-byte mode
  • Video-by-One Transmitter IP_8ch
    • Area: 0.98mm2 (1400um x 700um) including IO and ESD
    • Compliant with V-By-One HS 1.4 standard
    • Support 1/2/4/8-lane configuration
    • Support 3/4/5-byte mode
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