V-by-One/ LVDS Tx IP, Silicon Proven in SMIC 40LL
Overview
The V-by-One® HS technology aims to transmit video signals at a high data rate using internal equipment connections. The requirements to create a transmitter and receiver are laid out in the V-by-One®HS Standard. This has an available 8-lane PHY and 16-lane PHY for Tx and Rx, and it supports up to 4Gbps/lane. A transmitter for LVDS with a physical layer IP. This IP has 20 lanes (4 x 4D1C) of LVDS drivers and can handle 1.5Gbps of data rate.
Key Features
- LVDS compliant Tx
- 4 groups of 4-Data
- 1-Clock channels Each lane/group can be turned on/off individually Data/Clock can be assigned to any lane within the group
- Differential polarity can be flip per lane
- Supports from 168Mbps to 1.5Gbps data rate
- Supports reduced swing mode
- X7 Multiplier PLL for serial clock generation
- Configurable analog characteristics
- PLL loop filter
- PLL VCO gain
- Differential voltage Common-mode voltage
- Pre-emphasis strength
- Silicon Proven in SMIC 40nm LL
Block Diagram
Deliverables
- Datasheet
- Integration guideline
- GDSII or Phantom
- GDSII Layer map table
- CDL netlist for LVS
- LEF Verilog behaviour model
- Liberty timing model DRC/LVS/ERC results
Technical Specifications
Maturity
In Production
Availability
Immediate
Related IPs
- V-by-One/LVDS Rx IP, Silicon Proven in SMIC 40LL
- DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP)
- V-by-One Tx IP, Silicon Proven in SMIC 40LL
- DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
- DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
- JESD204B Tx-Rx PHY IP, Silicon Proven in SMIC 40LL