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SATA PHY IP

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Search (35)
Compare 35 SATA PHY IP from 14 vendors (1 - 10)
  • SATA 3 PHY
    • Serial ATA III Revision 3.3 compliant
    • Gen1i, Gen1m, Gen2i, Gen2m compliant
    • Gen1x, Gen2x compatible
    Block Diagram -- SATA 3 PHY
  • SATA PHY
    • Serial ATA II Revision 2.6 compliant
    • Gen1i, Gen1m, Gen2i, Gen2m compliant
    • Gen1x, Gen2x compatible
    • Initialization and power saving modes
    Block Diagram -- SATA PHY
  • USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP, Silicon Proven in UMC 28HPC
    • Compliant with PCIe 3.1 Base Specification
    • Compliant with Universal Serial Bus 3.2 Specification
    • Compliant with Universal Serial Bus 2.0 Specification
    • Compliant with UTMI 1.05 Specification
    Block Diagram -- USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP, Silicon Proven in UMC 28HPC
  • USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP
    • Compatible with PCIe/USB3/SATA base Specification
    • Fully compatible with PIPE3.1 interface specification
    • Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application
    • Support 16-bit or 32-bit parallel interface when encode/decode enabled
  • SATA 6G PHY in GF (40nm, 28nm)
    • Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
    • AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
    • AMBA 4 AXI and ACE-Lite bus interfaces
    • Memory data protection and memory address parity protection
  • SATA 6G PHY in UMC (40nm, 28nm, 22nm)
    • Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
    • AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
    • AMBA 4 AXI and ACE-Lite bus interfaces
    • Memory data protection and memory address parity protection
  • SATA 6G PHY in TSMC (40nm, 28nm, 16nm, 12nm, N7)
    • Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
    • AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
    • AMBA 4 AXI and ACE-Lite bus interfaces
    • Memory data protection and memory address parity protection
  • SATA 6G PHY in SMIC (40nm, 28nm)
    • Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
    • AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
    • AMBA 4 AXI and ACE-Lite bus interfaces
    • Memory data protection and memory address parity protection
  • Serial ATA (SATA) I/II PHY IP CORE
    • Supports 1.5 Gb/s (Gen 1) and 3.0 Gb/s (Gen 2) serial data rate
    • Compatible with Serial ATA II
    • Utilizes 10-bit or 20-bit parallel interface to transmit and receive Serial ATA data
    • Data and clock recovery from serial stream on the SATA bus
  • SATA/SAS 3.0 PHY
    • Highly customizable PMA configuration (controlled by PCS), X4 per Quad
    • Support SATA data rate 1.5/3/6Gbps
    • Support SAS data rate 1.5/3/6/12Gbps
    • Digitally-control-impedance termination resistors
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