GDDR IP

Compare 38 GDDR IP from 6 vendors (1 - 10)

GDDR7 Memory Controller
- Supports up to 40 Gbps per pin operation
- 2.5 GHz CK4 clock
- 1.25 GHz controller clock
- Internal data path 32x memory width (i.e. 256 bits for 8-bit memory)
- Optimized for high efficiency and low latency across a wide range of traffic scenarios (random/sequential, short/long bursts, etc.)
- Optimized command sequence for highest bus utilization including per-bank refresh scheduling: single queue structure handles look-ahead activates/ precharges and read/write ordering for minimal latency
GDDR6 Memory Controller IP
- JEDEC GDDR6 standard JESD250B
- Fast frequency switching
- Flexible Configuration
GDDR6 PHY IP for 12nm
- JEDEC JESD250 compliant GDDR6 support
- X16 mode, X8 mode, and pseudo-channel mode
- Low frequency RDQS mode support
GDDR7 PHY
- Highest performance at 36Gbp/s
- Fully hardened timing-closed PHY
- Available in multiple advanced-process nodes
- PAM3 signaling or NRZ
- 4 independent channels
- PHY independent mode
- Microcontroller or state machine training
- Low-power clock gating
GDDR6 PHY
- Single configuration supports one GDDR6 device per channel (coplanar) or two GDDR6 devices per channel (clamshell)
- DFI PHY Independent Mode for initialization and training
- Adaptive and continuous timing recovery
- Internal and external datapath loop-back modes
- Transmit crosstalk cancelation of immediate neighbors
- Per-bit DFE, CTLE, and FFE equalization
GDDR7 Synthesizable Transactor
- Supports GDDR7 memory devices from all leading vendors.
- Supports 100% of GDDR7 protocol draft JEDEC specification.
- Supports all the GDDR7 commands as per the specs.
- Supports 4 separate independent channels with point-to-point interface for data, address and command.
GDDR6 Synthesizable Transactor
- Supports 100% of GDDR6 protocol standard JESD250, JESD250A, JESD250B and JESD250C specification with version 3.12
- Supports all the GDDR6 commands as per the specs
- Supports 2 separate independent channels with point-to-point interface for data, address and command
- Supports double data rate (DDR) or quad data rate (QDR) data
GDDR5 Synthesizable Transactor
- Supports 100% of GDDR5 protocol standard JESD212C
- Supports all the GDDR5 commands as per the specs
- Supports all types of timing and protocol violation detection
- Supports up to 8GB device density
GDDR4 Synthesizable Transactor
- Supports 100% of GDDR4 protocol standard GDDR4Spec rev 04
- Supports all the GDDR4 commands as per the specs
- Supports all types of timing and protocol violation detection
- Supports all mode registers programming
GDDR3 Synthesizable Transactor
- Supports 100% of GDDR3 protocol standard
- Supports all the GDDR3 commands as per the specs
- Supports all types of timing and protocol violation detection
- Supports all mode registers programming