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PCI Express Phy IP for UMC

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Compare 23 PCI Express Phy IP for UMC from 6 vendors (1 - 10)
  • PCIe 2.0 PHY, UMC 40LP, x1
    • Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • PCIe L1 substate power management
    • Supports power gating and power island
    Block Diagram -- PCIe 2.0 PHY, UMC 40LP, x1
  • PCIe 2.0 PHY, UMC 40LP x4, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • PCIe L1 substate power management
    • Supports power gating and power island
    Block Diagram -- PCIe 2.0 PHY, UMC 40LP x4, North/South (vertical) poly orientation
  • PCIe 2.0 PHY, UMC 40LP x2, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • PCIe L1 substate power management
    • Supports power gating and power island
    Block Diagram -- PCIe 2.0 PHY, UMC 40LP x2, North/South (vertical) poly orientation
  • PCIe 2.0 PHY, UMC 28HPC+ x2, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • PCIe L1 substate power management
    • Supports power gating and power island
    Block Diagram -- PCIe 2.0 PHY, UMC 28HPC+ x2, North/South (vertical) poly orientation
  • PCIe 2.0 PHY, UMC 28HPC+ x1, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • PCIe L1 substate power management
    • Supports power gating and power island
    Block Diagram -- PCIe 2.0 PHY, UMC 28HPC+ x1, North/South (vertical) poly orientation
  • PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
    • Supports 2.5Gb/s serial data rate
    • Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
    • Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
    • Data and clock recovery from serial stream on the PCI Express bus
    Block Diagram -- PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
  • PCIe 3.0 PHY in UMC (12nm)
    • Physical coding sublayer (PCS) block with PIPE interface
    • Supports PCIe 3.1, 2.1, 1.1 encoding, backchannel initialization
    • Spread-spectrum clocking (SRIS)
    • Supports PCIe power management features, including L1 substate; power gating and power island; DFE bypass option and voltage mode Tx with under drive supply options
  • PCIe 3.0/3.1/USB3.0/SATA3 Combo PHY
    • Standard PHY interface enables multiple IP sources for PCI Express Logical Layer and provides a target interface for PCI Express PHY vendors.
    • Supports 2.5Gb/s only or 2.5Gb/s,5.0Gb/s and 8.0Gb/s serial data transmission rate
    • Utilizes 8-bit, 16-bit or 32- bit parallel interface to transmit and receive PCI Express data
    • Allows integration of high speed components into a single functional block as seen by the endpoint device designer.
  • PCIe 3.0 PHY in UMC (28nm)
    • Physical coding sublayer (PCS) block with PIPE interface
    • Supports PCIe 3.1, 2.1, 1.1 encoding, backchannel initialization
    • Spread-spectrum clocking (SRIS)
    • Supports PCIe power management features, including L1 substate; power gating and power island; DFE bypass option and voltage mode Tx with under drive supply options
  • PCIe 2.0 PHY in UMC (40nm, 28nm)
    • Physical coding sublayer (PCS) block with PIPE interface
    • Supports PCIe power management features, including L1 substate
    • Power gating for lowest standby power
    • Low active power using voltage mode TX with under drive supply options
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