PCI IP for UMC
Welcome to the ultimate PCI IP for UMC hub! Explore our vast directory of PCI IP for UMC
All offers in
PCI IP
for UMC
Filter
Compare
26
PCI IP
for UMC
from 8 vendors
(1
-
10)
-
PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- Supports 2.5Gb/s serial data rate
- Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
- Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
- Data and clock recovery from serial stream on the PCI Express bus
-
PCIe 2.0 PHY, UMC 40LP, x1
- Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- PCIe L1 substate power management
- Supports power gating and power island
-
PCIe 2.0 PHY, UMC 40LP x4, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- PCIe L1 substate power management
- Supports power gating and power island
-
PCIe 2.0 PHY, UMC 40LP x2, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- PCIe L1 substate power management
- Supports power gating and power island
-
PCIe 2.0 PHY, UMC 28HPC+ x2, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- PCIe L1 substate power management
- Supports power gating and power island
-
PCIe 2.0 PHY, UMC 28HPC+ x1, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- PCIe L1 substate power management
- Supports power gating and power island
-
PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- Complies with the PCI Express® Base 3.0 Specification, rev.3.1
- Supports Endpoint, Root-Port, Dual-Role, Switch configurations
- Supports x16, x8, x4, x2, x1 at Gen3, Gen2, Gen1 speeds
- Implements one Virtual Channel
-
PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface
- PCIe Interface
-
PCIe 3.0 PHY in UMC (12nm)
- Physical coding sublayer (PCS) block with PIPE interface
- Supports PCIe 3.1, 2.1, 1.1 encoding, backchannel initialization
- Spread-spectrum clocking (SRIS)
- Supports PCIe power management features, including L1 substate; power gating and power island; DFE bypass option and voltage mode Tx with under drive supply options
-
PCIe 3.0 PHY in UMC (28nm)
- Physical coding sublayer (PCS) block with PIPE interface
- Supports PCIe 3.1, 2.1, 1.1 encoding, backchannel initialization
- Spread-spectrum clocking (SRIS)
- Supports PCIe power management features, including L1 substate; power gating and power island; DFE bypass option and voltage mode Tx with under drive supply options