Cipher Accelerator IP for TSMC
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21
Cipher Accelerator IP
for TSMC
from 4 vendors
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TESIC RISC-V CC EAL5+ Secure Element Soft/Hard Macro
- CC EAL5+ secure microcontroller system
- CC EAL5+ secure cryptography
- CC EAL5+ security sensors
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TESIC CC EAL5+ Secure Element IP Core
- CC EAL5+ secure microcontroller system
- CC EAL5+ secure cryptography
- CC EAL5+ security sensors
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NIST FIPS-197 Compliant Ultra-Low Power AES IP Core
- Compliant to Advanced Encryption Standard (AES) (FIPS PUB 197).
- Supports both encryption and decryption functions.
- Supports 128/192/256-bit Cipher keys.
- Processes an 128-bit block in 480/582/684 clock cycles for 128/192/256-bits cipher keys respectively.
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802.11i CCMP/TKIP IP Core
- Small size:
- Includes key lookup, encryption, decryption, header parsing and modification, key expansion and data interface
- Uses external memory for key storage;
- Configurable number of keys supported; 64 bytes are required per bidirectional link
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IEEE 802.16e (WiMAX) AES Core
- Small size: from 8,900 ASIC gates at 802.16 data speeds
- Completely self-contained: does not require external memory
- Includes encryption, decryption, key expansion and data interface
- Support for Counter Mode Encryption (CTR) operation and CCM extensions (Counter Mode with CBC MAC)
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802.15.3 CCM AES Core
- Small size: From 9,500 ASIC gates at 802.15.3 data Speeds.
- High data rate: up to 8 Gbps for IEEE 802.15.3c / ECMA-387 (TC 48) / IEEE 802.11ad 60 GHz PHY
- Completely self-contained: does not require external memory
- Includes encryption, decryption, key expansion and data interface
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Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core
- Encrypts using the AES Rijndael Block Cipher Algorithm.
- Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST). FIPS-197 validated (AESAVS).
- Processes 128-bit data blocks with 8, 16 or 32-bit data interface
- Employs key sizes of 128 bits (AES128), 192, or 256 bits (AES256)
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802.11i CCM (CTR+CBC) AES Core for WiFi WLAN
- 8,900 ASIC gates at 802.11a/g OFDM data speeds
- Completely self-contained: does not require external memory
- Includes encryption, decryption, key expansion and data interface
- Support for Counter Mode Encryption (CTR) operation and CCM extensions (Counter Mode with CBC MAC, AES0CTR per NIST SP800-38C)
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AES-GCM Multi-channel upto 2Tbps Crypto Accelerator
- EXAMPLE CONFIGURATIONS
- The SafeXcel-IP-63 has a scalable number of processing pipes and channels. It is available in different configurations, suitable for different applications to meet different gate count and throughput objectives.
- • EIP-63a-c17-r
- o single pipe, 17 channels, register based (no memories)
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ChaCha20 Crypto Accelerator
- Wide bus interface
- 128-bits and 256-bits key sizes
- 32-bits counter and 64-bits counter modes
- CTR feedback mode