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SATA PHY IP for TSMC

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Compare 9 SATA PHY IP for TSMC from 6 vendors (1 - 9)
  • USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP
    • Compatible with PCIe/USB3/SATA base Specification
    • Fully compatible with PIPE3.1 interface specification
    • Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application
    • Support 16-bit or 32-bit parallel interface when encode/decode enabled
  • SATA 6G PHY in TSMC (40nm, 28nm, 16nm, 12nm, N7)
    • Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
    • AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
    • AMBA 4 AXI and ACE-Lite bus interfaces
    • Memory data protection and memory address parity protection
  • Serial ATA (SATA) I/II PHY IP CORE
    • Supports 1.5 Gb/s (Gen 1) and 3.0 Gb/s (Gen 2) serial data rate
    • Compatible with Serial ATA II
    • Utilizes 10-bit or 20-bit parallel interface to transmit and receive Serial ATA data
    • Data and clock recovery from serial stream on the SATA bus
  • PCIe 3.0/3.1/USB3.0/SATA3 Combo PHY
    • Standard PHY interface enables multiple IP sources for PCI Express Logical Layer and provides a target interface for PCI Express PHY vendors.
    • Supports 2.5Gb/s only or 2.5Gb/s,5.0Gb/s and 8.0Gb/s serial data transmission rate
    • Utilizes 8-bit, 16-bit or 32- bit parallel interface to transmit and receive PCI Express data
    • Allows integration of high speed components into a single functional block as seen by the endpoint device designer.
  • SATA 3.0 PHY
    • OOB Generation and Detection
    • Elasticity Buffer Optional
    • Alternative Host or Device Power-on Sequence State Machine
    • Speed Reduction Negotiation in Device Mode
  • SATA 6G PHY
    • ? 6-Gbps transmission rate through standard SATA cable
    • ? Spread-spectrum clock (SSC) generation and absorption
    • ? Programmable down-spread (+4,980 ppm through -4,980 ppm)
    • ? Fully clock-forwarded transceiver interface, configurable using soft PMA layer above hard macro PHY
  • USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 16FFC
    • Compatible with PCIe/USB3/SATA base Specification
    • Fully compatible with PIPE3.1 interface specification
    • Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application
    • Support 16-bit or 32-bit parallel interface when encode/decode enabled
  • 10Gbps XAUI Transceiver
    • 10Gbps XAUI optimised for BP applications.
    • Alternate independent channel support for FC and Gigabit Ethernet.
    • Per channel rate of 1 to 3.125Gb/s.
    • High speed differential Reference CK.
  • Quad 1 to 2.1Gb/s FC Transceiver
    • Quad SERDES designed for Fiber Channel Gigabit Ethernet applications. It has dual data rate 1.0625/2.125Gb/s. Jitter tolerance of 0.72UIpp and Jitter generation of 0.19UIpp. It has selectable pre-emphasis and equalizer. It has built in loopback, BIST function, comma detector. It needs 1.8V+/-5% for parallel IO and 2.5V+/-5% for high speed serial IO. It is a 324-pin PBGA with 500mW power per channel consumption.
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