Die to Die IP for TSMC
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Die to Die IP
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15
Die to Die IP
for TSMC
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- 3nm
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Universal Chiplet Interconnect Express (UCIe™) PHY
- Supports up to 32Gbps per pin including 4/8/12/16/24Gbps
- Forwarded clock, track, and valid pins
- Sideband messaging for link training and parameter exchange
- KGD (Known Good Die) testing capability
- Redundant lane repair (advanced)
- Width degradation (standard)
- Lane reversal
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UCIe-A PHY for Advanced Package (x64) in TSMC N3E, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
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UCIe-S PHY for Standard Package (x32) in TSMC N3P, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
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UCIe-S PHY for Standard Package (x32) in TSMC N3P, East/West Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
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UCIe-S PHY for Standard Package (x16) in TSMC N3E, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
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UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3)
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
- Side band channel for initialization and parameter exchange
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Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications
- High data rate of 2–24 Gb/s
- Very low power of < 0.375 pJ/bit @ 2–16 Gb/s 0.5-V VDDQ
- Very low latency of < 2 ns PHY-to-PHY
- Support for 2:1, 4:1, 8:1, 12:1 and 16:1 serialization and deserialization ratios
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Die-2-die interfaces for chiplets
- Analog I/Os
- ESD Power protection
- Ground pads
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INNOLINK-B PHY
- Support both Die2Die and Chip2Chip application
- GDDR6 like interface with IO voltage is core power supply (0.8V for TSMC 12nm)
- 24Gbps for maximum IO speed
- Default 16bit DQ Tx+ 16bit DQ Rx per module, module number can be 1/2/4/8/16 or more